Hi Prabhakar,
Thanks a lot for your comments!
> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2019年4月7日 18:49
> To: Z.q. Hou <zhiqiang....@nxp.com>; u-boot@lists.denx.de;
> albert.u.b...@aribaud.net; Priyanka Jain <priyanka.j...@nxp.com>; York Sun
> <york....@nxp.com>; sriram.d...@nxp.com;
> yamada.masah...@socionext.com; Mingkai Hu <mingkai...@nxp.com>; M.h.
> Lian <minghuan.l...@nxp.com>; bmeng...@gmail.com
> Subject: RE: [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries
> for PCIe
>
>
> > -----Original Message-----
> > From: Z.q. Hou
> > Sent: Monday, March 25, 2019 7:54 AM
> > To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; Priyanka Jain
> > <priyanka.j...@nxp.com>; York Sun <york....@nxp.com>;
> > sriram.d...@nxp.com; yamada.masah...@socionext.com; Prabhakar
> Kushwaha
> > <prabhakar.kushw...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>;
> M.h.
> > Lian <minghuan.l...@nxp.com>; bmeng...@gmail.com
> > Cc: Z.q. Hou <zhiqiang....@nxp.com>
> > Subject: [RESEND PATCHv4 2/9] armv8: lx2160a: add MMU table entries
> > for PCIe
> >
> > From: Hou Zhiqiang <zhiqiang....@nxp.com>
> >
> > The lx2160a have up to 6 PCIe controllers and have different address
> > and size of PCIe region.
> >
> > Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
> > ---
> > V4:
> > - No change
> >
> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12
> ++++++++++++
> > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 14
> > +++++++++++++-
> > 3 files changed, 27 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index 978d46b32f..2805e5f6f2 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -257,6 +257,18 @@ static struct mm_region final_map[] = {
> > PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> > PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
> > },
> > +#endif
> > +#ifdef CONFIG_ARCH_LX2160A
>
> Request to avoid SoC name in #ifdef. Use #ifdef SYS_PCIE5_PHYS_ADDR,
Yes, will change in next version.
Thanks,
Zhiqiang
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