On 4/9/19 9:02 PM, Simon Goldschmidt wrote: > The comment about SPL memory layout for socfpga gen5 is outdated: the > initial malloc memory is now at the end of the SRAM, gd is below it > (see board_init_f_alloc_reserve). > > Signed-off-by: Simon Goldschmidt <[email protected]> > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > include/configs/socfpga_common.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/include/configs/socfpga_common.h > b/include/configs/socfpga_common.h > index f9e2cdc1b3..32ee7426b6 100644 > --- a/include/configs/socfpga_common.h > +++ b/include/configs/socfpga_common.h > @@ -236,9 +236,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > * > * 0xFFFF_0000 ...... Start of SRAM > * 0xFFFF_xxxx ...... Top of stack (grows down) > - * 0xFFFF_yyyy ...... Malloc area > - * 0xFFFF_zzzz ...... Global Data > - * 0xFFFF_FF00 ...... End of SRAM > + * 0xFFFF_yyyy ...... Global Data > + * 0xFFFF_zzzz ...... Malloc area > + * 0xFFFF_FFFF ...... End of SRAM > * > * SRAM Memory layout for Arria 10: > * 0xFFE0_0000 ...... Start of SRAM (bottom) >
Acked-by: Marek Vasut <[email protected]> -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
