In case ocotp error bit is set, clear it.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm/mach-imx/imx8m/soc.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..7ec39b3e47 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -169,6 +169,7 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void)
{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* Init timer at very early state, because sscg pll setting
* will use it
@@ -180,6 +181,12 @@ int arch_cpu_init(void)
imx_set_wdog_powerdown(false);
}
+ if (is_imx8mq()) {
+ clock_enable(CCGR_OCOTP, 1);
+ if (readl(&ocotp->ctrl) & 0x200)
+ writel(0x200, &ocotp->ctrl_clr);
+ }
+
return 0;
}
--
2.16.4
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