Hi Lukas

Auer, Lukas <lukas.a...@aisec.fraunhofer.de> 於 2019年4月24日 週三 上午3:58寫道:
> Hi Rick,
> On Tue, 2019-04-23 at 13:42 +0800, Andes wrote:
> > From: Rick Chen <r...@andestech.com>
> >
> > In current RISC-V SMP flow, AE350 will encounter the the write
> > failure problem since hart_lottery and available_harts_lock was
> > not in ram address but in flash address when booing from flash.
> >
> > This patch can help to fix the failure problem when AE350 was
> > booting from flash by disable this two features.
> >
> Can you describe the issue you are seeing a bit more. The write
> failures are both to variables in the .data section, which should be
> writable. Perhaps the write failures can be avoided by moving the .data
> section or just the variable to RAM?

When I compile AE350's CONFIG_SYS_TEXT_BASE=0x80000000 which is spi flash base.
And burn u-boot.bin into AE350 spi flash. Power off / on, U-Boot will
run in XIP mode.
At this time prior_stage_fdt_address will be in flash address(0x8004e9e8)
So it is not writable.

80000042:       16021563                bnez    tp,800001ac
80000046:       0004f297                auipc   t0,0x4f
8000004a:       9a22a283                lw      t0,-1630(t0) #
8004e9e8 <prior_stage_fdt_address+0x3f74>
8000004e:       0092a023                sw      s1,0(t0)


> Thanks,
> Lukas
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