On 5/2/19 11:52 AM, Niel Fourie wrote:
[...]
> +++ b/board/phytec/phycore_am335x_r2/board.c
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * board.c
> + *
> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
> + *
> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +#include <common.h>
> +#include <spl.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/ddr_defs.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/sys_proto.h>
> +#include <fdtdec.h>
> +#include <power/tps65910.h>
> +#include <jffs2/load_kernel.h>
> +#include <mtd_node.h>
> +#include <fdt_support.h>
> +#include "board.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_SPL_BUILD
> +
> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
> +
> +#if CONFIG_IS_ENABLED(OS_BOOT)
> +int spl_start_uboot(void)
> +{
> + return 1;
Can this be removed completely ?
> +}
> +#endif
> +
> +/* DDR RAM defines */
> +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
> +
> +#define OSC (V_OSCK / 1000000)
> +const struct dpll_params dpll_ddr = {
> + DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
> +
> +const struct dpll_params *get_dpll_ddr_params(void)
> +{
> + return &dpll_ddr;
> +}
> +
> +const struct ctrl_ioregs ioregs = {
> + .cm0ioctl = 0x18B,
> + .cm1ioctl = 0x18B,
> + .cm2ioctl = 0x18B,
> + .dt0ioctl = 0x18B,
> + .dt1ioctl = 0x18B,
> +};
> +
> +static const struct cmd_control ddr3_cmd_ctrl_data = {
> + .cmd0csratio = 0x80,
> + .cmd0iclkout = 0x0,
> +
> + .cmd1csratio = 0x80,
> + .cmd1iclkout = 0x0,
> +
> + .cmd2csratio = 0x80,
> + .cmd2iclkout = 0x0,
> +};
> +
> +enum {
> + PHYCORE_R2_MT41K128M16JT_256MB,
> + PHYCORE_R2_MT41K256M16TW107IT_512MB,
> + PHYCORE_R2_MT41K512M16HA125IT_1024MB,
> +};
> +
> +struct am335x_sdram_timings {
> + struct emif_regs ddr3_emif_reg_data;
> + struct ddr_data ddr3_data;
> +};
> +
> +static struct am335x_sdram_timings physom_timings[] = {
> + [PHYCORE_R2_MT41K128M16JT_256MB] = {
> + .ddr3_emif_reg_data = {
> + .sdram_config = 0x61C052B2,
> + .ref_ctrl = 0x00000C30,
> + .sdram_tim1 = 0x0AAAD4DB,
> + .sdram_tim2 = 0x26437FDA,
> + .sdram_tim3 = 0x501F83FF,
> + .zq_config = 0x50074BE4,
> + .emif_ddr_phy_ctlr_1 = 0x7,
> + .ocp_config = 0x003d3d3d,
There's one tab too many .
> + },
> + .ddr3_data = {
> + .datardsratio0 = 0x36,
> + .datawdsratio0 = 0x38,
> + .datafwsratio0 = 0x99,
> + .datawrsratio0 = 0x73,
> + },
> + },
[...]
> +void scale_vcores_generic(int freq)
> +{
> + int sil_rev, mpu_vdd;
> +
> + /*
> + * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
> + * CORE voltage of 1.10V. For MPU voltage we need to switch based on
> + * the frequency we are running at.
> + */
> +#if defined(CONFIG_DM_I2C)
Can we not support non-DM i2c ?
> + if (power_tps65910_init(0))
> + return;
> +#else
And drop this part ?
> + if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
> + return;
> +#endif
[...]
--
Best regards,
Marek Vasut
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