On 5/6/19 10:13 PM, Simon Goldschmidt wrote:
[...]
> +static int socfpga_reset_bind(struct udevice *dev)
> +{
> + int ret;
> + struct udevice *sys_child;
> +
> + /*
> + * The sysreset driver does not have a device node, so bind it here.
> + * Bind it to the node, too, so that it can get its base address.
> + */
> + ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
> + dev->node, &sys_child);
> + if (ret)
> + debug("Warning: No sysreset driver: ret=%d\n", ret);
Can't we just fail here ? (return ret;) ?
> +
> + return 0;
> +}
> +
> static const struct udevice_id socfpga_reset_match[] = {
> { .compatible = "altr,rst-mgr" },
> { /* sentinel */ },
> @@ -141,6 +159,7 @@ U_BOOT_DRIVER(socfpga_reset) = {
> .name = "socfpga-reset",
> .id = UCLASS_RESET,
> .of_match = socfpga_reset_match,
> + .bind = socfpga_reset_bind,
> .probe = socfpga_reset_probe,
> .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
> .ops = &socfpga_reset_ops,
> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
> index 8ce3e2e207..5b8402ccae 100644
> --- a/drivers/sysreset/Kconfig
> +++ b/drivers/sysreset/Kconfig
> @@ -36,6 +36,20 @@ config SYSRESET_PSCI
> Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware
> must be running on your system.
>
> +config SYSRESET_SOCFPGA
> + bool "Enable support for Intel SOCFPGA family"
> + depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 ||
> TARGET_SOCFPGA_ARRIA10)
> + help
> + This enables the system reset driver support for Intel SOCFPGA SoCs
> + (Cyclone 5, Arria 5 and Arria 10).
> +
> +config SYSRESET_SOCFPGA_S10
> + bool "Enable support for Intel SOCFPGA Stratix 10"
> + depends on ARCH_SOCFPGA && TARGET_SOCFPGA_STRATIX10
> + help
> + This enables the system reset driver support for Intel SOCFPGA
> + Stratix SoCs.
> +
That sounds like two drivers => separate patch please.
[...]
> +static int socfpga_sysreset_request(struct udevice *dev,
> + enum sysreset_t type)
> +{
> + struct socfpga_sysreset_data *data = dev_get_priv(dev);
> +
> + switch (type) {
> + case SYSRESET_WARM:
> + writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
> + &data->rstmgr_base->ctrl);
> + break;
> + case SYSRESET_COLD:
> + writel(1 << RSTMGR_CTRL_SWCOLDRSTREQ_LSB,
> + &data->rstmgr_base->ctrl);
Use BIT() macro.
--
Best regards,
Marek Vasut
_______________________________________________
U-Boot mailing list
[email protected]
https://lists.denx.de/listinfo/u-boot
