Hi Christian,

On Thu, May 23, 2019 at 2:40 AM Simon Glass <s...@chromium.org> wrote:
>
> Hi Christian,
>
> On Wed, 22 May 2019 at 02:40, Christian Gmeiner
> <christian.gmei...@gmail.com> wrote:
> >
> > When using the coreboot target CONFIG_DM_SCSI gets set to y. This has the 
> > effect
> > that the current 'enable bus mastering' logic gets not compiled in. This 
> > change
>
> Where is it missing? Is it because U-Boot is not scanning the PCI bus?

If this is the case, we should fix similar issue on other devices, not
just only SATA.

>
> > fixes ahci problems I am seeing on an Intel Apollolake device.
> >
> > Signed-off-by: Christian Gmeiner <christian.gmei...@gmail.com>
> > ---
> >  drivers/ata/ahci.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >

Regards,
Bin
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