On Wed, 2019-05-22 at 00:09 -0700, Bin Meng wrote: > At present the link speed change callback is a nop. According to > macb device tree bindings, an optional "tx_clk" is used to clock > the ethernet controller's TX_CLK under different link speed. > > In 10/100 MII mode, transmit logic must be clocked from a free > running clock generated by the external PHY. In gigabit GMII mode, > the controller, not the external PHY, must generate the 125 MHz > transmit clock towards the PHY. > > Signed-off-by: Bin Meng <[email protected]> > > --- > > Changes in v2: > - add a comment for getting "tx_clk" via clk_get_by_name() > - does not change anything in the default case > - check the return value of clk_set_rate() > > drivers/net/macb.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) >
Successfully tested the series on a SiFive HiFive Unleashed board at 1000, 100, and 10 Mbps link rates. Reviewed-by: Lukas Auer <[email protected]> Tested-by: Lukas Auer <[email protected]> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
