Hi Bin
Bin Meng <[email protected]> 於 2019年6月4日 週二 上午10:48寫道：
>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes <[email protected]> wrote:
> >
> > From: Rick Chen <[email protected]>
> >
> > When L2 node exists inside cpus node, uclass_get_device
> > can not parse L2 node successfully. So move it outside
> > from cpus node.
> >
> > Also add tag-ram-ctl and data-ram-ctl attributes for
> > v5l2 cache controller driver. This can adjust timing
> > by requirement from dtb to improve performance.
> >
> > Signed-off-by: Rick Chen <[email protected]>
> > Cc: Greentime Hu <[email protected]>
> > ---
> > arch/riscv/dts/ae350_32.dts | 17 +++++++++++------
> > arch/riscv/dts/ae350_64.dts | 17 +++++++++++------
> > 2 files changed, 22 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
> > index cb6ee13..83abfcb 100644
> > --- a/arch/riscv/dts/ae350_32.dts
> > +++ b/arch/riscv/dts/ae350_32.dts
> > @@ -62,13 +62,18 @@
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > + };
> >
> > - L2: l2-cache@e0500000 {
> > - compatible = "cache";
> > - cache-level = <2>;
> > - cache-size = <0x40000>;
> > - reg = <0x0 0xe0500000 0x0 0x40000>;
> > - };
> > + L2: l2-cache@e0500000 {
> > + compatible = "cache";
>
> too generic compatible string (see my previous comments in patch [1/6])
Same replying in patch [1/6]
>
> > + cache-level = <2>;
> > + cache-size = <0x40000>;
> > + reg = <0xe0500000 0x40000>;
> > + andes,inst-prefetch = <3>;
> > + andes,data-prefetch = <3>;
> > + // The value format is <XRAMOCTL XRAMICTL>
>
> nits: no //, use /* */
OK
I will use /* */ instead of //
>
> > + andes,tag-ram-ctl = <0 0>;
> > + andes,data-ram-ctl = <0 0>;
> > };
> >
> > memory@0 {
> > diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
> > index 705491a..7009bdc 100644
> > --- a/arch/riscv/dts/ae350_64.dts
> > +++ b/arch/riscv/dts/ae350_64.dts
> > @@ -62,13 +62,18 @@
> > compatible = "riscv,cpu-intc";
> > };
> > };
> > + };
> >
> > - L2: l2-cache@e0500000 {
> > - compatible = "cache";
> > - cache-level = <2>;
> > - cache-size = <0x40000>;
> > - reg = <0x0 0xe0500000 0x0 0x40000>;
> > - };
> > + L2: l2-cache@e0500000 {
> > + compatible = "cache";
> > + cache-level = <2>;
> > + cache-size = <0x40000>;
> > + reg = <0x0 0xe0500000 0x0 0x40000>;
> > + andes,inst-prefetch = <3>;
> > + andes,data-prefetch = <3>;
> > + // The value format is <XRAMOCTL XRAMICTL>
>
> nits: no //, use /* */
I will use /* */ instead of //
Thanks
Rick
>
> > + andes,tag-ram-ctl = <0 0>;
> > + andes,data-ram-ctl = <0 0>;
> > };
> >
> > memory@0 {
> > --
>
> Regards,
> Bin
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