Hi Bin, Andy, On Mon, 17 Jun 2019 at 08:49, Andy Shevchenko <[email protected]> wrote: > > On Wed, Jun 12, 2019 at 10:07:11PM +0800, Bin Meng wrote: > > On Wed, Jun 12, 2019 at 9:49 PM Andy Shevchenko > > <[email protected]> wrote: > > > On Wed, Jun 12, 2019 at 04:23:37PM +0300, Andy Shevchenko wrote: > > > > On Wed, Jun 12, 2019 at 04:18:25PM +0300, Andy Shevchenko wrote: > > > > commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a > > > Author: Simon Glass <[email protected]> > > > Date: Thu Apr 25 21:59:06 2019 -0600 > > > > > > x86: Don't set up MTRRs in SPL > > > > > > > > > Please revert ASAP before release, thanks! > > > > So it looks that MTRRs are not programmed for Intel Edison to enable cache? > > > > Simon, would you please take a look? I suspect simply revert this will > > break the Chromebook SPL build? > > Since there is no activity on this and release is coming, I would propose to > revert for now.
I am OK with a revert for now if we don't have another solution. The problem here is that we want to select when the mtrrs are programmed. With my patch, this code is enabled on edison. I think the solution might be to set the mtrrs earlier on link. But I'll need to take a look and it won't be for about two weeks. Regards, Simon _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
