Dear "Mark Maestas", In message <[email protected]> you wrote: > > I am not having luck with watchdog enabled on the ppc4xx target. The > board is doing a reset before Linux gets a chance to load. I have added
Please define exactly what you mean by "before Linux gets a chance to load" - is it resetting in U-Boot, or after passsing control to the Linux kernel? > more WATCHDOG_RESET commands in the image file just to see if that helps What does "in the image file" mean? > and it does not seem to. Even though the reset function gets called it > is still getting reset. According to the ppc 440 documentation the By "reset function" you actually mean the code that is supposed to trigger the watchdog? Otherwise - the reset function is supposed to reset the system, so everthing would be OK then. > TSR[WIS] bit should get cleared to reset the timer and the code is doing > that. I don't understand why the board keeps resetting. This depends on the hardware, and obviously on the code doing this (keep in mind that using I/O accessors is mandatory these days). Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected] I haven't lost my mind -- it's backed up on tape somewhere. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
