Re: [U-Boot] [PATCH v3 12/57] ram: rk3399: Rename sys_reg with sys_reg2

[Kever Yang]

On 2019/7/16 下午7:57, Jagan Teki wrote:

Use dram config variable name as sys_reg2 instead of sys_reg
since the final variable value is to written into a pmugrf
register named as sys_reg2.

This reflect the both variable and associated register
names are same and also help to add next sys_reg's to
add it in future.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Signed-off-by: YouMin Chen <c...@rock-chips.com>

Reviewed-by: Kever Yang <kever.y...@rock-chips.com>

Thanks,
 - Kever

---
  drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++-------------
  1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/ram/rockchip/sdram_rk3399.c 
b/drivers/ram/rockchip/sdram_rk3399.c
index 2d3f0f6902..2ef969c07b 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1073,11 +1073,11 @@ static void set_ddrconfig(const struct chan_info *chan,
  static void dram_all_config(struct dram_info *dram,
                            const struct rk3399_sdram_params *params)
  {
-       u32 sys_reg = 0;
+       u32 sys_reg2 = 0;
        unsigned int channel, idx;

- sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);

-       sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
+       sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
+       sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);

for (channel = 0, idx = 0;

             (idx < params->base.num_channels) && (channel < 2);
@@ -1089,15 +1089,15 @@ static void dram_all_config(struct dram_info *dram,
                if (params->ch[channel].cap_info.col == 0)
                        continue;
                idx++;
-               sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
-               sys_reg |= SYS_REG_ENC_CHINFO(channel);
-               sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
-               sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
-               sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-               sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
-               sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
-               sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
-               sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+               sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, 
channel);
+               sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
+               sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
+               sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
+               sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
+               sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, 
channel);
+               sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, 
channel);
+               sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
+               sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);

ddr_msch_regs = dram->chan[channel].msch;

                noc_timing = &params->ch[channel].noc_timings;
@@ -1118,7 +1118,7 @@ static void dram_all_config(struct dram_info *dram,
                                     1 << 17);
        }

- writel(sys_reg, &dram->pmugrf->os_reg2);

+       writel(sys_reg2, &dram->pmugrf->os_reg2);
        rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
                     params->base.stride << 10);

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