This extracts Intel Bay Trail based board specific information from README.x86, converts plain text documentation to reST format and adds them to Sphinx TOC tree. No essential content change.
Signed-off-by: Bin Meng <bmeng...@gmail.com> --- doc/README.x86 | 75 ------------------------------------------- doc/board/intel/bayleybay.rst | 29 +++++++++++++++++ doc/board/intel/index.rst | 2 ++ doc/board/intel/minnowmax.rst | 70 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 75 deletions(-) create mode 100644 doc/board/intel/bayleybay.rst create mode 100644 doc/board/intel/minnowmax.rst diff --git a/doc/README.x86 b/doc/README.x86 index 8077ff3..b4f0f7c 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -226,81 +226,6 @@ to the last 2MB of the 8MB chip, address range [600000, 7FFFFF]. --- -Intel Bay Trail based board instructions for bare mode: - -This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. -Two boards that use this configuration are Bayley Bay and Minnowboard MAX. -Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at -the time of writing). Put it in the corresponding board directory and rename -it to fsp.bin. - -Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same -board directory as vga.bin. - -You still need two more binary blobs. For Bayley Bay, they can be extracted -from the sample SPI image provided in the FSP (SPI.bin at the time of writing). - - $ ./tools/ifdtool -x BayleyBay/SPI.bin - $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin - $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin - -For Minnowboard MAX, we can reuse the same ME firmware above, but for flash -descriptor, we need get that somewhere else, as the one above does not seem to -work, probably because it is not designed for the Minnowboard MAX. Now download -the original firmware image for this board from: - -http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip - -Unzip it: - - $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip - -Use ifdtool in the U-Boot tools directory to extract the images from that -file, for example: - - $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin - -This will provide the descriptor file - copy this into the correct place: - - $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin - -Now you can build U-Boot and obtain u-boot.rom -Note: below are examples/information for Minnowboard MAX. - -$ make minnowmax_defconfig -$ make all - -Checksums are as follows (but note that newer versions will invalidate this): - -$ md5sum -b board/intel/minnowmax/*.bin -ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin -69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin -894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin -a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin - -The ROM image is broken up into these parts: - -Offset Description Controlling config ------------------------------------------------------------- -000000 descriptor.bin Hard-coded to 0 in ifdtool -001000 me.bin Set by the descriptor -500000 <spare> -6ef000 Environment CONFIG_ENV_OFFSET -6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE -700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE -7b0000 vga.bin CONFIG_VGA_BIOS_ADDR -7c0000 fsp.bin CONFIG_FSP_ADDR -7f8000 <spare> (depends on size of fsp.bin) -7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 - -Overall ROM image size is controlled by CONFIG_ROM_SIZE. - -Note that the debug version of the FSP is bigger in size. If this version -is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of -the default value 0xfffc0000. - ---- - Intel Cherry Hill specific instructions for bare mode: This uses Intel FSP for Braswell platform. Download it from Intel FSP website, diff --git a/doc/board/intel/bayleybay.rst b/doc/board/intel/bayleybay.rst new file mode 100644 index 0000000..db97f64 --- /dev/null +++ b/doc/board/intel/bayleybay.rst @@ -0,0 +1,29 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng <bmeng...@gmail.com> + +Bayley Bay CRB +============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Bayley Bay, they can be extracted +from the sample SPI image provided in the FSP (SPI.bin at the time of writing):: + + $ ./tools/ifdtool -x BayleyBay/SPI.bin + $ cp flashregion_0_flashdescriptor.bin board/intel/bayleybay/descriptor.bin + $ cp flashregion_2_intel_me.bin board/intel/bayleybay/me.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make bayleybay_defconfig + $ make all + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst index 93b8ba2..af24760 100644 --- a/doc/board/intel/index.rst +++ b/doc/board/intel/index.rst @@ -6,4 +6,6 @@ Intel .. toctree:: :maxdepth: 2 + bayleybay crownbay + minnowmax diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst new file mode 100644 index 0000000..0281217 --- /dev/null +++ b/doc/board/intel/minnowmax.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Simon Glass <s...@chromium.org> + +Minnowboard MAX +=============== + +This uses as FSP as with Crown Bay, except it is for the Atom E3800 series. +Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at +the time of writing). Put it in the corresponding board directory and rename +it to fsp.bin. + +Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same +board directory as vga.bin. + +You still need two more binary blobs. For Minnowboard MAX, we can reuse the +same ME firmware above, but for flash descriptor, we need get that somewhere +else, as the one above does not seem to work, probably because it is not +designed for the Minnowboard MAX. Now download the original firmware image +for this board from: + + * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Unzip it:: + + $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip + +Use ifdtool in the U-Boot tools directory to extract the images from that +file, for example:: + + $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin + +This will provide the descriptor file - copy this into the correct place:: + + $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make minnowmax_defconfig + $ make all + +Checksums are as follows (but note that newer versions will invalidate this):: + + $ md5sum -b board/intel/minnowmax/*.bin + ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin + 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin + 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin + a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin + +The ROM image is broken up into these parts: + +====== ================== ============================ +Offset Description Controlling config +====== ================== ============================ +000000 descriptor.bin Hard-coded to 0 in ifdtool +001000 me.bin Set by the descriptor +500000 <spare> +6ef000 Environment CONFIG_ENV_OFFSET +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE +700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE +7b0000 vga.bin CONFIG_VGA_BIOS_ADDR +7c0000 fsp.bin CONFIG_FSP_ADDR +7f8000 <spare> (depends on size of fsp.bin) +7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16 +====== ================== ============================ + +Overall ROM image size is controlled by CONFIG_ROM_SIZE. + +Note that the debug version of the FSP is bigger in size. If this version +is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of +the default value 0xfffc0000. -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
