From: Rick Chen <r...@andestech.com>
Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.
In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.
Signed-off-by: Rick Chen <r...@andestech.com>
Cc: KC Lin <kc...@andestech.com>
---
drivers/cache/Kconfig | 9 +++
drivers/cache/Makefile | 1 +
drivers/cache/cache-v5l2.c | 186 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 196 insertions(+)
create mode 100644 drivers/cache/cache-v5l2.c
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
ARMv7(32-bit) devices. The driver configures the cache settings
found in the device tree.
+config V5L2_CACHE
+ bool "Andes V5L2 cache driver"
+ select CACHE
+ depends on RISCV_NDS_CACHE
+ help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_CACHE) += cache-uclass.o
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 0000000..d367171
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <r...@andestech.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/ofnode.h>
+
+struct l2cache {
+ volatile u64 configure;
+ volatile u64 control;
+ volatile u64 hpm0;
+ volatile u64 hpm1;
+ volatile u64 hpm2;
+ volatile u64 hpm3;
+ volatile u64 error_status;
+ volatile u64 ecc_error;
+ volatile u64 cctl_command0;
+ volatile u64 cctl_access_line0;
+ volatile u64 cctl_command1;
+ volatile u64 cctl_access_line1;
+ volatile u64 cctl_command2;
+ volatile u64 cctl_access_line2;
+ volatile u64 cctl_command3;
+ volatile u64 cctl_access_line4;
+ volatile u64 cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE 0x1
+/* prefetch */
+#define IPREPETCH_OFF 3
+#define DPREPETCH_OFF 5
+#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF 8
+#define TRAMICTL_OFF 10
+#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF 11
+#define DRAMICTL_OFF 13
+#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+ struct l2cache *regs;
+ u32 iprefetch;
+ u32 dprefetch;
+ u32 tram_ctl[2];
+ u32 dram_ctl[2];
+};
+
+static int v5l2_enable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+
+ if (regs)
+ setbits_le32(®s->control, L2_ENABLE);
+
+ return 0;
+}
+
+static int v5l2_disable(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ volatile struct l2cache *regs = plat->regs;
+ u8 hart = gd->arch.boot_hart;
+ void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+ if ((regs) && (readl(®s->control) & L2_ENABLE)) {
+ writel(L2_WBINVAL_ALL, cctlcmd);
+
+ while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
+ if ((readl(®s->cctl_status) &
CCTL_STATUS_ILLEGAL(hart))) {
+ printf("L2 flush illegal! hanging...");
+ hang();
+ }
+ }
+ clrbits_le32(®s->control, L2_ENABLE);
+ }
+
+ return 0;
+}
+
+static int v5l2_ofdata_to_platdata(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct l2cache *regs;
+
+ regs = (struct l2cache *)dev_read_addr(dev);
+ plat->regs = regs;
+
+ plat->iprefetch = -EINVAL;
+ plat->dprefetch = -EINVAL;
+ plat->tram_ctl[0] = -EINVAL;
+ plat->dram_ctl[0] = -EINVAL;
+
+ /* Instruction and data fetch prefetch depth */
+ dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
+ dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
+
+ /* Set tag RAM and data RAM setup and output cycle */
+ dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
+ dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
+
+ return 0;
+}
+
+static int v5l2_probe(struct udevice *dev)
+{
+ struct v5l2_plat *plat = dev_get_platdata(dev);
+ struct l2cache *regs = plat->regs;
+ u32 ctl_val;
+
+ ctl_val = readl(®s->control);
+
+ if (!(ctl_val & L2_ENABLE))
+ ctl_val |= L2_ENABLE;
+
+ if (plat->iprefetch != -EINVAL) {
+ ctl_val &= ~(IPREPETCH_MSK);
+ ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
+ }
+
+ if (plat->dprefetch != -EINVAL) {
+ ctl_val &= ~(DPREPETCH_MSK);
+ ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
+ }
+
+ if (plat->tram_ctl[0] != -EINVAL) {
+ ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
+ ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
+ ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
+ }
+
+ if (plat->dram_ctl[0] != -EINVAL) {
+ ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
+ ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
+ ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
+ }
+
+ writel(ctl_val, ®s->control);
+
+ return 0;
+}
+
+static const struct udevice_id v5l2_cache_ids[] = {
+ { .compatible = "v5l2cache" },
+ {}
+};
+
+static const struct cache_ops v5l2_cache_ops = {
+ .enable = v5l2_enable,
+ .disable = v5l2_disable,
+};
+
+U_BOOT_DRIVER(v5l2_cache) = {
+ .name = "v5l2_cache",
+ .id = UCLASS_CACHE,
+ .of_match = v5l2_cache_ids,
+ .ofdata_to_platdata = v5l2_ofdata_to_platdata,
+ .probe = v5l2_probe,
+ .platdata_auto_alloc_size = sizeof(struct v5l2_plat),
+ .ops = &v5l2_cache_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
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