Ashish Kumar <ashish.ku...@nxp.com> schrieb am Mi., 11. Sep. 2019, 10:49:
> > > > -----Original Message----- > > From: Vignesh Raghavendra <vigne...@ti.com> > > Sent: Tuesday, September 10, 2019 10:36 PM > > To: Jagan Teki <ja...@openedev.com> > > Cc: Vignesh Raghavendra <vigne...@ti.com>; u-boot@lists.denx.de; Tom > > Rini <tr...@konsulko.com>; Eugeniy Paltsev > > <eugeniy.palt...@synopsys.com>; alexey.brod...@synopsys.com; Ashish > > Kumar <ashish.ku...@nxp.com> > > Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable > > SPI_NOR_4B_OPCODES for n25q512* and n25q256* > > > > Caution: EXT Email > > > > Not all variants of n25q256* and n25q512* support 4 Byte stateless > > addressing opcodes and there is no easy way to discover at runtime > whether > > the flash supports this feature or not. > > Therefore don't set SPI_NOR_4B_OPCODES for these flashes. > Hi Vignesh, > > I think it will be good to keep it here and disable this for boards by > using not set flag in config > Like > # SPI_NOR_4B_OPCODES is not set > I'd prefer to take this patch, as this is what Linux does. I think it's better to have an opt-in option. That way, all chips work with the default settings (even if that means some chips don't use 4 baste opcodes even if they could). Still, so we have such an op-in possibility to enable 4 byte opcodes on these chips? Regards, Simon > Regards > Ashish > > > > Signed-off-by: Vignesh Raghavendra <vigne...@ti.com> For n25q512ax3: > > Tested-by: Eugeniy Paltsev <palt...@synopsys.com> > > --- > > drivers/mtd/spi/spi-nor-ids.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/mtd/spi/spi-nor-ids.c > b/drivers/mtd/spi/spi-nor-ids.c > > index f32a6c7d464b..5a7fe07c8309 100644 > > --- a/drivers/mtd/spi/spi-nor-ids.c > > +++ b/drivers/mtd/spi/spi-nor-ids.c > > @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = { > > { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | > > SPI_NOR_QUAD_READ) }, > > { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | > > SPI_NOR_QUAD_READ) }, > > { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | > > SPI_NOR_QUAD_READ) }, > > - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | > > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > > { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | > > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > - { INFO("mt25qu512a (n25q512a)", 0x20bb20, 0, 64 * 1024, 1024, > > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > USE_FSR | > > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > > + { INFO("mt25qu512a (n25q512a)", 0x20bb20, 0, 64 * 1024, 1024, > > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, > > + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | > > + USE_FSR | SPI_NOR_QUAD_READ) }, > > { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | > USE_FSR | > > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | > USE_FSR | > > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | > USE_FSR | > > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > > -- > > 2.23.0 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot