> -----Original Message----- > From: Stefan Roese <[email protected]> > Sent: Wednesday, September 11, 2019 11:17 AM > To: Schrempf Frieder <[email protected]>; Ashish Kumar > <[email protected]>; Ye Li <[email protected]>; > [email protected] > Cc: Fabio Estevam <[email protected]>; [email protected]; dl- > uboot-imx <[email protected]> > Subject: Re: [U-Boot] [EXT] Re: [PATCH 1/6] spi: fsl_qspi: Fix DDR mode > setting for latest iMX platforms > > Caution: EXT Email > > Hi Ashish, > Hi Frieder, > > On 09.09.19 10:10, Schrempf Frieder wrote: > > Hi Ashish, > > > > On 27.08.19 11:56, Ashish Kumar wrote: > >> > >> > >>> -----Original Message----- > >>> From: Schrempf Frieder <[email protected]> > >>> Sent: Wednesday, August 14, 2019 5:41 PM > >>> To: Ashish Kumar <[email protected]>; Ye Li <[email protected]>; > >>> [email protected] > >>> Cc: Fabio Estevam <[email protected]>; [email protected]; > dl- > >>> uboot-imx <[email protected]> > >>> Subject: Re: [EXT] Re: [U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR > >>> mode setting for latest iMX platforms > >>> > >>> Caution: EXT Email > >>> > >>> Sorry, I hit the "Send" button too early ;) > >>> > >>> On 14.08.19 14:07, Frieder Schrempf wrote: > >>>> Hi Ashish, > >>>> > >>>> On 14.08.19 14:02, Ashish Kumar wrote: > >>>>> > >>>>> > >>>>>> -----Original Message----- > >>>>>> From: U-Boot <[email protected]> On Behalf Of > Schrempf > >>>>>> Frieder > >>>>>> Sent: Wednesday, August 14, 2019 5:07 PM > >>>>>> To: Ye Li <[email protected]>; [email protected] > >>>>>> Cc: Fabio Estevam <[email protected]>; u- > [email protected]; > >>> dl- > >>>>>> uboot-imx <[email protected]> > >>>>>> Subject: [EXT] Re: [U-Boot] [PATCH 1/6] spi: fsl_qspi: Fix DDR > >>>>>> mode setting for latest iMX platforms > >>>>>> > >>>>>> Caution: EXT Email > >>>>>> > >>>>>> Hi Ye, > >>>>>> > >>>>>> On 14.08.19 12:08, Ye Li wrote: > >>>>>>> On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI > >>>>>>> controller is updated to have TDH field in FLSHCR register. > >>>>>>> According to reference manual, this TDH must be set to 1 when > >>> DDR_EN is set. > >>>>>>> Otherwise, the TX DDR delay logic won't be enabled. > >>>>>> > >>>>>> This is actually an issue I have experienced myself. But in our > >>>>>> case this behavior only happened on i.MX6ULL not on i.MX6UL. > >>>>>> Either the QSPI controller hardware or the BootROM code changed > >>>>>> when moving from UL to ULL. For details see: [1]. > >>>>>> > >>>>>>> > >>>>>>> Another issue in DDR mode is the MCR register will be > >>>>>>> overwritten in every read/write/erase operation. This causes > >>>>>>> DDR_EN been cleared while TDH=1, then no clk2x output for TX > >>>>>>> data shift and all operations will fail. > >>>>>> > >>>>>> The best way to fix all of these things (also the ones in the > >>>>>> other > >>>>>> patches) would be to fix them in Linux and port the driver from > >>>>>> Linux to U- Boot. Actually I've already done most of the porting > >>>>>> [2], > >>>>> Hello Frieder, > >>>>> > >>>>> I had tested your porting and it was not functional on u-boot. > >>>>> I found that only erase, read up to TX/RX buf size is working or > >>>>> something like that. > >>>>> Also ip and AHB mode cannot be used at time in code. Previously > >>>>> only IP mode was used in u-boot, Since endianness across different > >>>>> QSPI-IP(ls1012, ls1043, ls1021 big endian), (ls1088,ls2088 little > >>>>> endian) is not consistent on various silicon's. I am not sure if > >>>>> Yogesh who worked with you on Linux porting gave you this > >>>>> information about endianness inconsistency. > >>>> > >>>> Ok, thanks for your feedback. The endianness for the different SoCs > >>>> can be handled by the device data. > >>> > >>> Does this work correctly in Linux, or does the Linux driver need fixes? > >>> > >>>> > >>>>> Please suggest way forward. How to correct this issue? > >>> > >>> The first thigh would be to make sure the Linux driver works for all > >>> platforms and then do the porting to U-Boot. I will be out of office > >>> for > >>> 10 days. After that I can try to work on this, but I need support > >>> and testing for other platforms. I only have i.MX6UL/ULL. > >> > >> Hi Frieder, > >> > >> I have found some break though after porting to 2019.10 and few > modification in driver code, I will update in a weeks' time. Please do not > invest time on this. > >> If I need some help I will update. > > > > Thanks for your work. Do you already have some news? Can you share > > your results? > > I'm most likely currently running in similar issues on tests with the i.MX6ULL > EVK. QSPI does not work reliably. So before digging deeper into the QSPI > driver, I wanted to check on the status of any updates in the driver. Is there > anything available that I could use for testing already? Hi Stefan, Frieder,
The spi-mem version is still under debug, I could make it working for ls1088rdb, ls1046rdb, but it is failing for ls1012ardb and ls2088ardb and untested for i.mx and other Layerscape silicon/boards . It is derived from work done by Frieder earlier. This version can be found here: https://github.com/erashish007/u-boot-spi-mem/tree/spi-mem-port There is completely working version of fsl_qspi.c based on old xfer method, which was not accepted in upstream, considering it is recommended to migrate to spi-mem frame. This version is located here: https://github.com/erashish007/u-boot-spi-mem/tree/xfer_wrking Regards Ashish I have push the working version of these on github. > > Thanks, > Stefan _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
