st 11. 9. 2019 v 16:45 odesÃlatel Michal Simek <michal.si...@xilinx.com> napsal: > > From: T Karthik Reddy <t.karthik.re...@xilinx.com> > > Phy setup should be done before dwc3 soft core reset as it is done > in linux & this fixes unreliable detection of usb cable on host side. > > Signed-off-by: T Karthik Reddy <t.karthik.re...@xilinx.com> > Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com> > Signed-off-by: Michal Simek <michal.si...@xilinx.com> > --- > > drivers/usb/dwc3/core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 56e2a046bf06..2498f0efb1a4 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -440,6 +440,8 @@ static int dwc3_core_init(struct dwc3 *dwc) > goto err0; > } > > + dwc3_phy_setup(dwc); > + > ret = dwc3_core_soft_reset(dwc); > if (ret) > goto err0; > @@ -514,8 +516,6 @@ static int dwc3_core_init(struct dwc3 *dwc) > > dwc3_writel(dwc->regs, DWC3_GCTL, reg); > > - dwc3_phy_setup(dwc); > - > ret = dwc3_alloc_scratch_buffers(dwc); > if (ret) > goto err0; > -- > 2.17.1 >
Haven't got any reply on this and patchwork assigned it to me that's why I am applying it. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot