On Fri, Sep 27, 2019 at 6:43 AM Vignesh Raghavendra <[email protected]> wrote: > > Newer variants of mt25q* flashes support 4 Byte addressing opcodes. Add > entries for the same. These flashes have bit 6 set in 5th byte of READ ID > response. > > Signed-off-by: Vignesh Raghavendra <[email protected]>
Tested-by: Simon Goldschmidt <[email protected]> I tested read ,write and erase on socfpga gen5 with n25q256a and mt25ql256a. Regards, Simon > --- > drivers/mtd/spi/spi-nor-ids.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index bb67661b40d2..c7b6cf002c54 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = { > { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | > SPI_NOR_QUAD_READ) }, > { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | > SPI_NOR_QUAD_READ) }, > { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | > SPI_NOR_QUAD_READ) }, > + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K > | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, > + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | > SPI_NOR_QUAD_READ) }, > { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) > }, > { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR > | SPI_NOR_QUAD_READ) }, > + { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | > USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, > { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR > | SPI_NOR_QUAD_READ) }, > { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR > | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR > | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, > -- > 2.23.0 > _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
