Hi Simon, On 01/10/19 11:58 AM, Simon Goldschmidt wrote: > On Tue, Oct 1, 2019 at 6:58 AM <[email protected]> wrote: >> >> >> >> On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote: >>> External E-Mail >>> >>> >>> Older variants of n25q256* and n25q512* do not support 4 Byte stateless >> >> nit: drop "older variants of". Looks like the latest datasheet still require >> ENTER and EXIT 4-byte address mode commands. > > Hm, the datasheet I'm looking at [1] lists 4-byte opcodes. I don't know if all > required types are supported, but I would think so. >
Note 14 at the end of Table 18: Command Set of Datasheet[1] that you pointed out says 4-BYTE PAGE PROGRAM(0x12) is only supported only on specific variants of n25q* flashes. So best bet is to disable 4 Byte opcodes for all variants of n25q unless we find a way to detect flashes that actually support those opcodes at runtime. Regards Vignesh > Reviewed-by: Simon Goldschmidt <[email protected]> > > [1] > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf > > Regards, > Simon > >> >>> addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these >>> entries. >>> >>> Signed-off-by: Vignesh Raghavendra <[email protected]> >> >> Reviewed-by: Tudor Ambarus <[email protected]> >> >>> --- >>> drivers/mtd/spi/spi-nor-ids.c | 8 ++++---- >>> 1 file changed, 4 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c >>> index df0643ed1d47..bb67661b40d2 100644 >>> --- a/drivers/mtd/spi/spi-nor-ids.c >>> +++ b/drivers/mtd/spi/spi-nor-ids.c >>> @@ -161,12 +161,12 @@ const struct flash_info spi_nor_ids[] = { >>> { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | >>> SPI_NOR_QUAD_READ) }, >>> { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | >>> SPI_NOR_QUAD_READ) }, >>> { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | >>> SPI_NOR_QUAD_READ) }, >>> - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | >>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >>> - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | >>> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >>> + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | >>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, >>> + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | >>> SPI_NOR_QUAD_READ) }, >>> { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, >>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) >>> }, >>> - { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >>> - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >>> + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ) }, >>> + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ) }, >>> { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, >>> { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, >>> { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR >>> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, >>> -- Regards Vignesh _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
