On Wed, Sep 04, 2019 at 04:01:39PM +0530, Lokesh Vutla wrote: > The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs) > in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP > Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional > 288 KB of L2 configurable SRAM/Cache. These subsystems do not have > an MMU but contain a Region Address Translator (RAT) sub-module for > translating 32-bit processor addresses into larger bus addresses. > The inter-processor communication between the main A72 cores and > these processors is achieved through shared memory and Mailboxes. > Add the DT nodes for these DSP processor sub-systems in the common > k3-j721e-main.dtsi file. > > Signed-off-by: Suman Anna <s-a...@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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