On Wed, Sep 04, 2019 at 04:01:37PM +0530, Lokesh Vutla wrote: > The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) > subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within > the MCU domain, and the remaining two clusters are present in the > MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be > configured at boot time to be either run in a LockStep mode or in > an Asymmetric Multi Processing (AMP) fashion in Split-mode. These > subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal > memories for each core split between two banks - ATCM and BTCM > (further interleaved into two banks). There are some IP integration > differences from standard Arm R5 clusters such as the absence of > an ACP port, presence of an additional TI-specific Region Address > Translater (RAT) module for translating 32-bit CPU addresses into > larger system bus addresses etc. > > Add the DT node for the MCU domain R5F cluster/subsystem, the two > R5 cores are added as child nodes to the main cluster/subsystem node. > The cluster is configured to run in LockStep mode by default, with the > ATCMs enabled to allow the R5 cores to execute code from DDR with > boot-strapping code from ATCM. The inter-processor communication > between the main A72 cores and these processors is achieved through > shared memory and Mailboxes. > > Signed-off-by: Suman Anna <s-a...@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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