Improve the IRQ response latency by setting GIC root clock source to
sys_pll2_200m from osc.
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 5c3f780127..04903510f0 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -806,6 +806,12 @@ int clock_init(void)
clock_enable(CCGR_TSENSOR, 1);
clock_enable(CCGR_OCOTP, 1);
+ /* config GIC ROOT to sys_pll2_200m */
+ clock_enable(CCGR_GIC, 0);
+ clock_set_target_val(GIC_CLK_ROOT,
+ CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+ clock_enable(CCGR_GIC, 1);
+
return 0;
}
#endif
--
2.16.4
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