From: YouMin Chen <c...@rock-chips.com>
sdram.h is more for rk3288, rename it to sdram_rk3288.h;
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
clean the related file who has use the header file at the same time.
Signed-off-by: YouMin Chen <c...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sdram.h | 223 +++++++++++-------
.../include/asm/arch-rockchip/sdram_common.h | 147 ------------
.../include/asm/arch-rockchip/sdram_rk3288.h | 102 ++++++++
arch/arm/mach-rockchip/Makefile | 2 +-
arch/arm/mach-rockchip/rk3036/rk3036.c | 2 +-
arch/arm/mach-rockchip/rk3288/rk3288.c | 2 +-
.../mach-rockchip/{sdram_common.c => sdram.c} | 2 +-
drivers/ram/rockchip/dmc-rk3368.c | 2 +-
drivers/ram/rockchip/sdram_debug.c | 2 +-
drivers/ram/rockchip/sdram_rk3128.c | 2 +-
drivers/ram/rockchip/sdram_rk3188.c | 2 +-
drivers/ram/rockchip/sdram_rk322x.c | 2 +-
drivers/ram/rockchip/sdram_rk3288.c | 2 +-
drivers/ram/rockchip/sdram_rk3328.c | 2 +-
drivers/ram/rockchip/sdram_rk3399.c | 2 +-
15 files changed, 248 insertions(+), 248 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-rockchip/sdram_common.h
create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3288.h
rename arch/arm/mach-rockchip/{sdram_common.c => sdram.c} (99%)
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h
b/arch/arm/include/asm/arch-rockchip/sdram.h
index 9220763fa7..3866d0b4d4 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -1,102 +1,147 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (c) 2015 Google, Inc
- *
- * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*/
-#ifndef _ASM_ARCH_RK3288_SDRAM_H__
-#define _ASM_ARCH_RK3288_SDRAM_H__
+#ifndef _ASM_ARCH_SDRAM_COMMON_H
+#define _ASM_ARCH_SDRAM_COMMON_H
-struct rk3288_sdram_channel {
- /*
- * bit width in address, eg:
- * 8 banks using 3 bit to address,
- * 2 cs using 1 bit to address.
- */
- u8 rank;
- u8 col;
- u8 bk;
- u8 bw;
- u8 dbw;
- u8 row_3_4;
- u8 cs0_row;
- u8 cs1_row;
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
+enum {
+ DDR4 = 0,
+ DDR3 = 0x3,
+ LPDDR2 = 0x5,
+ LPDDR3 = 0x6,
+ LPDDR4 = 0x7,
+ UNUSED = 0xFF
+};
+
+struct sdram_cap_info {
+ unsigned int rank;
+ /* dram column number, 0 means this channel is invalid */
+ unsigned int col;
+ /* dram bank number, 3:8bank, 2:4bank */
+ unsigned int bk;
+ /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int bw;
+ /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+ unsigned int dbw;
/*
- * For of-platdata, which would otherwise convert this into two
- * byte-swapped integers. With a size of 9 bytes, this struct will
- * appear in of-platdata as a byte array.
- *
- * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+ * row_3_4 = 1: 6Gb or 12Gb die
+ * row_3_4 = 0: normal die, power of 2
*/
- u8 dummy;
-#endif
+ unsigned int row_3_4;
+ unsigned int cs0_row;
+ unsigned int cs1_row;
+ unsigned int ddrconfig;
};
-struct rk3288_sdram_pctl_timing {
- u32 togcnt1u;
- u32 tinit;
- u32 trsth;
- u32 togcnt100n;
- u32 trefi;
- u32 tmrd;
- u32 trfc;
- u32 trp;
- u32 trtw;
- u32 tal;
- u32 tcl;
- u32 tcwl;
- u32 tras;
- u32 trc;
- u32 trcd;
- u32 trrd;
- u32 trtp;
- u32 twr;
- u32 twtr;
- u32 texsr;
- u32 txp;
- u32 txpdll;
- u32 tzqcs;
- u32 tzqcsi;
- u32 tdqs;
- u32 tcksre;
- u32 tcksrx;
- u32 tcke;
- u32 tmod;
- u32 trstl;
- u32 tzqcl;
- u32 tmrr;
- u32 tckesr;
- u32 tdpd;
+struct sdram_base_params {
+ unsigned int ddr_freq;
+ unsigned int dramtype;
+ unsigned int num_channels;
+ unsigned int stride;
+ unsigned int odt;
};
-check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
-struct rk3288_sdram_phy_timing {
- u32 dtpr0;
- u32 dtpr1;
- u32 dtpr2;
- u32 mr[4];
-};
+/*
+ * sys_reg bitfield struct
+ * [31] row_3_4_ch1
+ * [30] row_3_4_ch0
+ * [29:28] chinfo
+ * [27] rank_ch1
+ * [26:25] col_ch1
+ * [24] bk_ch1
+ * [23:22] cs0_row_ch1
+ * [21:20] cs1_row_ch1
+ * [19:18] bw_ch1
+ * [17:16] dbw_ch1;
+ * [15:13] ddrtype
+ * [12] channelnum
+ * [11] rank_ch0
+ * [10:9] col_ch0
+ * [8] bk_ch0
+ * [7:6] cs0_row_ch0
+ * [5:4] cs1_row_ch0
+ * [3:2] bw_ch0
+ * [1:0] dbw_ch0
+ */
+#define SYS_REG_DDRTYPE_SHIFT 13
+#define DDR_SYS_REG_VERSION 2
+#define SYS_REG_DDRTYPE_MASK 7
+#define SYS_REG_NUM_CH_SHIFT 12
+#define SYS_REG_NUM_CH_MASK 1
+#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
+#define SYS_REG_ROW_3_4_MASK 1
+#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
+#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
+#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
+ SYS_REG_NUM_CH_SHIFT)
+#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
+#define SYS_REG_RANK_MASK 1
+#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
+ SYS_REG_RANK_SHIFT(ch))
+#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
+#define SYS_REG_COL_MASK 3
+#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
+#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
+#define SYS_REG_BK_MASK 1
+#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
+ SYS_REG_BK_SHIFT(ch))
+#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK 3
+#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK 3
+#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
+#define SYS_REG_BW_MASK 3
+#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
+#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
+#define SYS_REG_DBW_MASK 3
+#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
-struct rk3288_base_params {
- u32 noc_timing;
- u32 noc_activate;
- u32 ddrconfig;
- u32 ddr_freq;
- u32 dramtype;
- /*
- * DDR Stride is address mapping for DRAM space
- * Stride Ch 0 range Ch1 range Total
- * 0x00 0-256MB 256MB-512MB 512MB
- * 0x05 0-1GB 0-1GB 1GB
- * 0x09 0-2GB 0-2GB 2GB
- * 0x0d 0-4GB 0-4GB 4GB
- * 0x17 N/A 0-4GB 4GB
- * 0x1a 0-4GB 4GB-8GB 8GB
- */
- u32 stride;
- u32 odt;
-};
+#define SYS_REG_ENC_VERSION(n) ((n) << 28)
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (5 + 2 * (ch)); \
+ } while (0)
+
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+ (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+ (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+ (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+ (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+ (4 + 2 * (ch)); \
+ } while (0)
+
+#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) <<
SYS_REG_CS1_COL_SHIFT(ch))
+
+/* Get sdram size decode from reg */
+size_t rockchip_sdram_size(phys_addr_t reg);
+
+/* Called by U-Boot board_init_r for Rockchip SoCs */
+int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+ struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
deleted file mode 100644
index 8027b53636..0000000000
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
- */
-
-#ifndef _ASM_ARCH_SDRAM_COMMON_H
-#define _ASM_ARCH_SDRAM_COMMON_H
-
-enum {
- DDR4 = 0,
- DDR3 = 0x3,
- LPDDR2 = 0x5,
- LPDDR3 = 0x6,
- LPDDR4 = 0x7,
- UNUSED = 0xFF
-};
-
-struct sdram_cap_info {
- unsigned int rank;
- /* dram column number, 0 means this channel is invalid */
- unsigned int col;
- /* dram bank number, 3:8bank, 2:4bank */
- unsigned int bk;
- /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int bw;
- /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
- unsigned int dbw;
- /*
- * row_3_4 = 1: 6Gb or 12Gb die
- * row_3_4 = 0: normal die, power of 2
- */
- unsigned int row_3_4;
- unsigned int cs0_row;
- unsigned int cs1_row;
- unsigned int ddrconfig;
-};
-
-struct sdram_base_params {
- unsigned int ddr_freq;
- unsigned int dramtype;
- unsigned int num_channels;
- unsigned int stride;
- unsigned int odt;
-};
-
-/*
- * sys_reg bitfield struct
- * [31] row_3_4_ch1
- * [30] row_3_4_ch0
- * [29:28] chinfo
- * [27] rank_ch1
- * [26:25] col_ch1
- * [24] bk_ch1
- * [23:22] cs0_row_ch1
- * [21:20] cs1_row_ch1
- * [19:18] bw_ch1
- * [17:16] dbw_ch1;
- * [15:13] ddrtype
- * [12] channelnum
- * [11] rank_ch0
- * [10:9] col_ch0
- * [8] bk_ch0
- * [7:6] cs0_row_ch0
- * [5:4] cs1_row_ch0
- * [3:2] bw_ch0
- * [1:0] dbw_ch0
-*/
-#define SYS_REG_DDRTYPE_SHIFT 13
-#define DDR_SYS_REG_VERSION 2
-#define SYS_REG_DDRTYPE_MASK 7
-#define SYS_REG_NUM_CH_SHIFT 12
-#define SYS_REG_NUM_CH_MASK 1
-#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
-#define SYS_REG_ROW_3_4_MASK 1
-#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
-#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
-#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch))
-#define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT)
-#define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \
- SYS_REG_NUM_CH_SHIFT)
-#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
-#define SYS_REG_RANK_MASK 1
-#define SYS_REG_ENC_RANK(n, ch) (((n) - SYS_REG_RANK_MASK) << \
- SYS_REG_RANK_SHIFT(ch))
-#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
-#define SYS_REG_COL_MASK 3
-#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << SYS_REG_COL_SHIFT(ch))
-#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
-#define SYS_REG_BK_MASK 1
-#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
- SYS_REG_BK_SHIFT(ch))
-#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
-#define SYS_REG_CS0_ROW_MASK 3
-#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
-#define SYS_REG_CS1_ROW_MASK 3
-#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
-#define SYS_REG_BW_MASK 3
-#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
-#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
-#define SYS_REG_DBW_MASK 3
-#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
-
-#define SYS_REG_ENC_VERSION(n) ((n) << 28)
-#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
- (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
- (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
- (5 + 2 * (ch)); \
- } while (0)
-
-#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
- (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
- (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
- (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
- (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
- (4 + 2 * (ch)); \
- } while (0)
-
-#define SYS_REG_CS1_COL_SHIFT(ch) (0 + 2 * (ch))
-#define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) <<
SYS_REG_CS1_COL_SHIFT(ch))
-
-/* Get sdram size decode from reg */
-size_t rockchip_sdram_size(phys_addr_t reg);
-
-/* Called by U-Boot board_init_r for Rockchip SoCs */
-int dram_init(void);
-
-#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
-inline void sdram_print_dram_type(unsigned char dramtype)
-{
-}
-
-inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base)
-{
-}
-
-inline void sdram_print_stride(unsigned int stride)
-{
-}
-#else
-void sdram_print_dram_type(unsigned char dramtype);
-void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
- struct sdram_base_params *base);
-void sdram_print_stride(unsigned int stride);
-#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
-
-#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h
b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h
new file mode 100644
index 0000000000..9220763fa7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_RK3288_SDRAM_H__
+#define _ASM_ARCH_RK3288_SDRAM_H__
+
+struct rk3288_sdram_channel {
+ /*
+ * bit width in address, eg:
+ * 8 banks using 3 bit to address,
+ * 2 cs using 1 bit to address.
+ */
+ u8 rank;
+ u8 col;
+ u8 bk;
+ u8 bw;
+ u8 dbw;
+ u8 row_3_4;
+ u8 cs0_row;
+ u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /*
+ * For of-platdata, which would otherwise convert this into two
+ * byte-swapped integers. With a size of 9 bytes, this struct will
+ * appear in of-platdata as a byte array.
+ *
+ * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+ */
+ u8 dummy;
+#endif
+};
+
+struct rk3288_sdram_pctl_timing {
+ u32 togcnt1u;
+ u32 tinit;
+ u32 trsth;
+ u32 togcnt100n;
+ u32 trefi;
+ u32 tmrd;
+ u32 trfc;
+ u32 trp;
+ u32 trtw;
+ u32 tal;
+ u32 tcl;
+ u32 tcwl;
+ u32 tras;
+ u32 trc;
+ u32 trcd;
+ u32 trrd;
+ u32 trtp;
+ u32 twr;
+ u32 twtr;
+ u32 texsr;
+ u32 txp;
+ u32 txpdll;
+ u32 tzqcs;
+ u32 tzqcsi;
+ u32 tdqs;
+ u32 tcksre;
+ u32 tcksrx;
+ u32 tcke;
+ u32 tmod;
+ u32 trstl;
+ u32 tzqcl;
+ u32 tmrr;
+ u32 tckesr;
+ u32 tdpd;
+};
+check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
+
+struct rk3288_sdram_phy_timing {
+ u32 dtpr0;
+ u32 dtpr1;
+ u32 dtpr2;
+ u32 mr[4];
+};
+
+struct rk3288_base_params {
+ u32 noc_timing;
+ u32 noc_activate;
+ u32 ddrconfig;
+ u32 ddr_freq;
+ u32 dramtype;
+ /*
+ * DDR Stride is address mapping for DRAM space
+ * Stride Ch 0 range Ch1 range Total
+ * 0x00 0-256MB 256MB-512MB 512MB
+ * 0x05 0-1GB 0-1GB 1GB
+ * 0x09 0-2GB 0-2GB 2GB
+ * 0x0d 0-4GB 0-4GB 4GB
+ * 0x17 N/A 0-4GB 4GB
+ * 0x1a 0-4GB 4GB-8GB 8GB
+ */
+ u32 stride;
+ u32 odt;
+};
+
+#endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 45d9b06233..a9563ade4f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
-obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c
b/arch/arm/mach-rockchip/rk3036/rk3036.c
index be458cfb64..e9ada6dea3 100644
--- a/arch/arm/mach-rockchip/rk3036/rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/rk3036.c
@@ -43,7 +43,7 @@ void board_debug_uart_init(void)
#if !CONFIG_IS_ENABLED(RAM)
/*
* When CONFIG_RAM is enabled, the dram_init() function is implemented
- * in sdram_common.c.
+ * in sdram.c.
*/
int dram_init(void)
{
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c
b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 057ce92080..3e84523379 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -15,7 +15,7 @@
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/qos_rk3288.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-rockchip/sdram_common.c
b/arch/arm/mach-rockchip/sdram.c
similarity index 99%
rename from arch/arm/mach-rockchip/sdram_common.c
rename to arch/arm/mach-rockchip/sdram.c
index 22a4aca940..acb1af765e 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -7,7 +7,7 @@
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/ram/rockchip/dmc-rk3368.c
b/drivers/ram/rockchip/dmc-rk3368.c
index e52fc3baad..9df8f8f4af 100644
--- a/drivers/ram/rockchip/dmc-rk3368.c
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -17,7 +17,7 @@
#include <asm/arch-rockchip/grf_rk3368.h>
#include <asm/arch-rockchip/ddr_rk3368.h>
#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3288.h>
struct dram_info {
struct ram_info info;
diff --git a/drivers/ram/rockchip/sdram_debug.c
b/drivers/ram/rockchip/sdram_debug.c
index 9cf662675b..133d1938d5 100644
--- a/drivers/ram/rockchip/sdram_debug.c
+++ b/drivers/ram/rockchip/sdram_debug.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <debug_uart.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
void sdram_print_dram_type(unsigned char dramtype)
{
diff --git a/drivers/ram/rockchip/sdram_rk3128.c
b/drivers/ram/rockchip/sdram_rk3128.c
index bfabc22a7d..8486653c6f 100644
--- a/drivers/ram/rockchip/sdram_rk3128.c
+++ b/drivers/ram/rockchip/sdram_rk3128.c
@@ -9,7 +9,7 @@
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3128.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
struct dram_info {
struct ram_info info;
diff --git a/drivers/ram/rockchip/sdram_rk3188.c
b/drivers/ram/rockchip/sdram_rk3188.c
index 00e52ec949..d3e4316ef0 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -21,7 +21,7 @@
#include <asm/arch-rockchip/grf_rk3188.h>
#include <asm/arch-rockchip/pmu_rk3188.h>
#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3288.h>
#include <linux/err.h>
struct chan_info {
diff --git a/drivers/ram/rockchip/sdram_rk322x.c
b/drivers/ram/rockchip/sdram_rk322x.c
index 94893e17cf..223f048161 100644
--- a/drivers/ram/rockchip/sdram_rk322x.c
+++ b/drivers/ram/rockchip/sdram_rk322x.c
@@ -17,7 +17,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/sdram_rk322x.h>
#include <asm/arch-rockchip/uart.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/types.h>
#include <linux/err.h>
diff --git a/drivers/ram/rockchip/sdram_rk3288.c
b/drivers/ram/rockchip/sdram_rk3288.c
index 5775254007..690751d074 100644
--- a/drivers/ram/rockchip/sdram_rk3288.c
+++ b/drivers/ram/rockchip/sdram_rk3288.c
@@ -21,7 +21,7 @@
#include <asm/arch-rockchip/grf_rk3288.h>
#include <asm/arch-rockchip/pmu_rk3288.h>
#include <asm/arch-rockchip/sdram.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3288.h>
#include <linux/err.h>
#include <power/regulator.h>
#include <power/rk8xx_pmic.h>
diff --git a/drivers/ram/rockchip/sdram_rk3328.c
b/drivers/ram/rockchip/sdram_rk3328.c
index e84c9be6a2..e7919337ea 100644
--- a/drivers/ram/rockchip/sdram_rk3328.c
+++ b/drivers/ram/rockchip/sdram_rk3328.c
@@ -14,7 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3328.h>
#include <asm/arch-rockchip/grf_rk3328.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3328.h>
#include <asm/arch-rockchip/uart.h>
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index ed70137ce7..9b7de4ae41 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -18,7 +18,7 @@
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/pmu_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
-#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_rk3399.h>
#include <linux/err.h>
#include <time.h>
--
2.17.1
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