Am 15.10.2019 um 22:10 schrieb Simon Goldschmidt:
This is an RFC series with the target to move SPL code from arch to DM drivers.
I've sent a few patches of this series now as non-RFC, as I don't know if I will make it this merge window: I still have trouble getting the existing defconfigs into the 64 KB of SRAM for SPL :-(
Might need some work regarding size of DM in SPL... Regards, Simon
It is not finished, but I send this here for discussion mainly about the devicetree format with the goal of keeping the various sub- architectures (cyclone5, arria10, etc.) in the same style. Patch 8 adds a C tool to convert existing gen5 qts handoff files to a handoff dtsi. As an example, the last patch contains the handoff dtsi for socfpga_socrates. I have sent v1 some time ago, but this one has heavily changed and is not finished, thus v2 but RFC. This series also is not edited to fix patman warnings, yet. Changes in v2: - add dts based reset handling (messed up in v1) - split this patch from v1 5/6 - split this patch from v1 5/6 Simon Goldschmidt (18): ddr: socfpga: gen5: constify altera_gen5_sdram_ops dts: arm: socfpga: add label for clkmgr arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN timer: dw-apb: add reset handling arm: socfpga: gen5: move initial reset handling to reset driver arm: dts: socfpga: add settings for gen5 clk driver arm: dts: socfpga: make clock nodes available in SPL socfpga: gen5: add new tool to create handoff dtsi files sdram: socfpga: gen5: make config structs dts compatible ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata' ddr: socfpga: gen5: read handoff information from devicetree arm: socfpga: gen5: add readonly clk driver arm: socfpga: gen5: enable DM CLK arm: socfpga: gen5: move clock initialization to CLK driver arm: socfpga: gen5: load CLK config from devicetree spi: cadence_qspi: support DM_CLK arm: socfpga: gen5: parse qspi clock from devictree socfpga: gen5: move CLK and SDRAM to DM MAINTAINERS | 1 + arch/arm/dts/socfpga-common-u-boot.dtsi | 71 ++ arch/arm/dts/socfpga.dtsi | 7 +- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 1 + .../socfpga_cyclone5_socrates_handoff.dtsi | 290 +++++++ arch/arm/mach-socfpga/Kconfig | 4 +- arch/arm/mach-socfpga/Makefile | 5 - arch/arm/mach-socfpga/clock_manager.c | 31 +- arch/arm/mach-socfpga/clock_manager_gen5.c | 528 ------------- arch/arm/mach-socfpga/create_handoff_gen5.c | 660 ++++++++++++++++ arch/arm/mach-socfpga/freeze_controller.c | 10 +- .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_gen5.h | 14 - .../mach-socfpga/include/mach/sdram_gen5.h | 16 +- arch/arm/mach-socfpga/qts-to-handoff.sh | 83 +++ arch/arm/mach-socfpga/reset_manager_gen5.c | 13 - arch/arm/mach-socfpga/spl_gen5.c | 29 +- arch/arm/mach-socfpga/wrap_pll_config.c | 146 ---- arch/arm/mach-socfpga/wrap_sdram_config.c | 318 -------- drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-gen5.c | 705 ++++++++++++++++++ drivers/ddr/altera/sdram_gen5.c | 92 ++- drivers/ddr/altera/sequencer.c | 74 +- drivers/ddr/altera/sequencer.h | 9 +- drivers/reset/reset-socfpga.c | 37 +- drivers/spi/cadence_qspi.c | 20 +- drivers/timer/dw-apb-timer.c | 18 +- include/configs/socfpga_common.h | 5 - 28 files changed, 2072 insertions(+), 1118 deletions(-) create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates_handoff.dtsi delete mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c create mode 100644 arch/arm/mach-socfpga/create_handoff_gen5.c create mode 100755 arch/arm/mach-socfpga/qts-to-handoff.sh delete mode 100644 arch/arm/mach-socfpga/wrap_pll_config.c delete mode 100644 arch/arm/mach-socfpga/wrap_sdram_config.c create mode 100644 drivers/clk/altera/clk-gen5.c
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
