Hi, We need to follow the TRM sequence and settings to ensure that the DPLL & PHY operates correctly over the entire temperature range.
Tested with SATA on dra7-evm. Since this is a bug fix, I will suggest to include it in current -rc. cheers, -roger Roger Quadros (4): phy: ti-pipe3: Use TRM recommended settings for SATA DPLL phy: ti-pipe3: Introduce mode property in driver data phy: ti-pipe3: improve DPLL stability for SATA & USB phy: ti-pipe3: Fix SATA & USB PHY power up sequence drivers/phy/ti-pipe3-phy.c | 281 ++++++++++++++++++++++++++++++++----- 1 file changed, 249 insertions(+), 32 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
