From: Shreesha Rajashekar <shreesha.rajashe...@broadcom.com>
Add iproc spi/qspi driver for Broadcom iproc
architecture based soc's.
Signed-off-by: Shreesha Rajashekar <shreesha.rajashe...@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.go...@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyanni...@broadcom.com>
---
drivers/spi/Kconfig | 26 +
drivers/spi/Makefile | 4 +
drivers/spi/iproc_qspi.c | 1161 ++++++++++++++++++++++++++++++++++++++
drivers/spi/iproc_qspi.h | 47 ++
drivers/spi/iproc_spi.c | 71 +++
5 files changed, 1309 insertions(+)
create mode 100644 drivers/spi/iproc_qspi.c
create mode 100644 drivers/spi/iproc_qspi.h
create mode 100644 drivers/spi/iproc_spi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8588866489..b18f26d61a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -405,6 +405,32 @@ config DAVINCI_SPI
help
Enable the Davinci SPI driver
+config IPROC_SPI
+ bool "SPI support for iproc soc's"
+ help
+ This selects the iproc SPI controller.
+ The controller is used in iProc SoCs.
+
+config IPROC_PL022_SPI
+ bool "ARM PL022 SPI driver"
+ select IPROC_SPI
+ help
+ Enable the ARM PL022 (SPI) driver for iproc architecture soc's.
+
+config IPROC_QSPI
+ bool "QSPI driver for BCM iProc QSPI Controller"
+ select IPROC_SPI
+ help
+ This selects the BCM iProc QSPI controller.
+ This driver support spi flash single, quad and memory reads.
+
+config BCM_IPROC_USE_BSPI
+ bool "Broadcom BSPI driver for fast read"
+ depends on IPROC_QSPI
+ help
+ This selects the BCM BSPI driver for fast read mode.
+ Enable this mode if flash(nand/nor) supports.
+
config SH_SPI
bool "SuperH SPI driver"
depends on DEPRECATED
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ae4f2958f8..2388bc6e93 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,10 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
obj-$(CONFIG_ICH_SPI) += ich.o
+ifndef CONFIG_DM_SPI
+obj-$(CONFIG_IPROC_SPI) += iproc_spi.o
+endif
+obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
new file mode 100644
index 0000000000..20ca94d4f3
--- /dev/null
+++ b/drivers/spi/iproc_qspi.c
@@ -0,0 +1,1161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 Broadcom.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include "iproc_qspi.h"
+
+#define QSPI_AXI_CLK 175000000 /* 175MHz */
+
+/* default SCK frequency, unit: HZ */
+#define QSPI_DEF_SCK_FREQ 50000000
+
+#ifndef CONFIG_DM_SPI
+/* Configurations */
+#ifndef IPROC_QSPI_BUS
+#error IPROC_QSPI_BUS not defined
+#endif /* !IPROC_QSPI_BUS */
+#ifndef IPROC_QSPI_CS
+#error CONFIG_IPROC_QSPI_CS not defined
+#endif /* !IPROC_QSPI_CS */
+#endif
+#define QSPI_WAIT_TIMEOUT_MS 200U /* msec */
+
+/* Chip attributes */
+#define QSPI_REG_BASE IPROC_QSPI_BASE_REG
+#define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG
+#define SPBR_MIN 8U
+#define SPBR_MAX 255U
+#define NUM_TXRAM 32U
+#define NUM_RXRAM 32U
+#define NUM_CDRAM 16U
+
+#define CDRAM_PCS0 2
+#define CDRAM_CONT BIT(7)
+#define CDRAM_BITS_EN BIT(6)
+#define CDRAM_QUAD_MODE BIT(8)
+#define CDRAM_RBIT_INPUT BIT(10)
+
+#define MSPI_SPE BIT(6)
+#define MSPI_CONT_AFTER_CMD BIT(7)
+
+/*
+ * Register fields
+ */
+#define MSPI_SPCR0_MSB_BITS_8 0x00000020
+#define BSPI_RAF_CONTROL_START_MASK 0x00000001
+#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
+#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
+#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x00010000
+#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0
+#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16
+#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3
+#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1
+#define BSPI_STRAP_OVERRIDE_SHIFT 0
+
+/*
+ * Flash opcode and parameters
+ */
+#define OPCODE_RDSR 0x05
+#define OPCODE_FAST_READ 0x0B
+#define OPCODE_DUAL_READ 0x3b
+#define OPCODE_QUAD_READ 0x6b
+#define OPCODE_EN4B 0xB7
+#define OPCODE_EX4B 0xE9
+#define OPCODE_BRWR 0x17
+
+/*
+ * Check dual/quad mode configurations
+ */
+#ifndef CONFIG_DM_SPI
+#if (IPROC_BSPI_DATA_LANES >= 1) && (IPROC_BSPI_DATA_LANES <= 4)
+#if IPROC_BSPI_DATA_LANES == 3
+#error Nubmer of lanes should be 1, 2 or 4.
+#endif /* IPROC_BSPI_DATA_LANES == 3 */
+#else /* 1 <= IPROC_BSPI_DATA_LANES <= 4 */
+#error Nubmer of lanes should be 1, 2 or 4.
+#endif
+#if (IPROC_BSPI_ADDR_LANES >= 1) && (IPROC_BSPI_ADDR_LANES <= 4)
+#if IPROC_BSPI_ADDR_LANES == 3
+#error Nubmer of lanes should be 1, 2 or 4.
+#endif /* IPROC_BSPI_ADDR_LANES == 3 */
+#else /* 1 <= IPROC_BSPI_ADDR_LANES <= 4 */
+#error Nubmer of lanes should be 1, 2 or 4.
+#endif
+#endif
+
+/* MSPI registers */
+#define MSPI_SPCR0_LSB_REG 0x000
+#define MSPI_SPCR0_MSB_REG 0x004
+#define MSPI_SPCR1_LSB_REG 0x008
+#define MSPI_SPCR1_MSB_REG 0x00c
+#define MSPI_NEWQP_REG 0x010
+#define MSPI_ENDQP_REG 0x014
+#define MSPI_SPCR2_REG 0x018
+#define MSPI_STATUS_REG 0x020
+#define MSPI_CPTQP_REG 0x024
+#define MSPI_TXRAM_REG 0x040
+#define MSPI_RXRAM_REG 0x0c0
+#define MSPI_CDRAM_REG 0x140
+#define MSPI_WRITE_LOCK_REG 0x180
+#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
+
+/* BSPI registers */
+#define BSPI_REVISION_ID_REG 0x000
+#define BSPI_SCRATCH_REG 0x004
+#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
+#define BSPI_BUSY_STATUS_REG 0x00c
+#define BSPI_INTR_STATUS_REG 0x010
+#define BSPI_B0_STATUS_REG 0x014
+#define BSPI_B0_CTRL_REG 0x018
+#define BSPI_B1_STATUS_REG 0x01c
+#define BSPI_B1_CTRL_REG 0x020
+#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024
+#define BSPI_FLEX_MODE_ENABLE_REG 0x028
+#define BSPI_BITS_PER_CYCLE_REG 0x02C
+#define BSPI_BITS_PER_PHASE_REG 0x030
+#define BSPI_CMD_AND_MODE_BYTE_REG 0x034
+#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038
+#define BSPI_XOR_VALUE_REG 0x03C
+#define BSPI_XOR_ENABLE_REG 0x040
+#define BSPI_PIO_MODE_ENABLE_REG 0x044
+#define BSPI_PIO_IODIR_REG 0x048
+#define BSPI_PIO_DATA_REG 0x04C
+
+/* RAF registers */
+#define BSPI_RAF_START_ADDRESS_REG 0x00
+#define BSPI_RAF_NUM_WORDS_REG 0x04
+#define BSPI_RAF_CTRL_REG 0x08
+#define BSPI_RAF_FULLNESS_REG 0x0C
+#define BSPI_RAF_WATERMARK_REG 0x10
+#define BSPI_RAF_STATUS_REG 0x14
+#define BSPI_RAF_READ_DATA_REG 0x18
+#define BSPI_RAF_WORD_CNT_REG 0x1C
+#define BSPI_RAF_CURR_ADDR_REG 0x20
+
+/*
+ * Register access macros
+ */
+#define REG_RD(x) readl(x)
+#define REG_WR(x, y) writel((y), (x))
+#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y))
+#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y))
+
+/* State */
+enum bcm_qspi_state {
+ QSPI_STATE_DISABLED,
+ QSPI_STATE_MSPI,
+ QSPI_STATE_BSPI
+};
+
+/* QSPI platform data */
+struct bcmspi_platdata {
+ /* Registers */
+ s32 frequency;
+ void *mspi_hw;
+ void *bspi_hw;
+ void *bspi_hw_raf;
+};
+
+/* QSPI private data */
+struct bcmspi_priv {
+#ifndef CONFIG_DM_SPI
+ /* Slave entry */
+ struct spi_slave slave;
+#endif
+ /* Specified SPI parameters */
+ unsigned int max_hz;
+ unsigned int spi_mode;
+
+ /* State */
+ enum bcm_qspi_state state;
+ u8 bspi_op;
+ u32 bspi_addr;
+ int mspi_16bit;
+ int mode_4byte;
+
+ /* Registers */
+ void *mspi_hw;
+ void *bspi_hw;
+ void *bspi_hw_raf;
+ void *cru_hw;
+};
+
+#ifndef CONFIG_DM_SPI
+/* Macro to get the private data */
+#define to_qspi_slave(s) container_of(s, struct bcmspi_priv, slave)
+
+int iproc_qspi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus == IPROC_QSPI_BUS && cs == IPROC_QSPI_CS)
+ return 1;
+ return 0;
+}
+
+struct spi_slave *iproc_qspi_setup_slave(unsigned int bus,
+ unsigned int cs,
+ unsigned int max_hz,
+ unsigned int mode)
+{
+ struct bcmspi_priv *priv;
+ unsigned int spbr;
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ pr_err("Wrong QSPI bus (%d) cs (%d)!\n", bus, cs);
+ return NULL;
+ }
+
+ priv = (struct bcmspi_priv *)spi_alloc_slave(struct bcmspi_priv,
+ bus, cs);
+ if (!priv) {
+ pr_err("No memory for QSPI slave!\n");
+ return NULL;
+ }
+
+ priv->max_hz = max_hz;
+ priv->spi_mode = mode;
+ priv->slave.mode = mode;
+ priv->state = QSPI_STATE_DISABLED;
+ priv->mode_4byte = 0;
+ priv->bspi_hw = (void *)(QSPI_REG_BASE + 0x000);
+ priv->bspi_hw_raf = (void *)(QSPI_REG_BASE + 0x100);
+ priv->mspi_hw = (void *)(QSPI_REG_BASE + 0x200);
+ priv->cru_hw = (void *)CRU_CONTROL_REG;
+
+ /* BSPI: clock configuration */
+ REG_CLR(priv->cru_hw, 0x00000006);
+ REG_RD(priv->cru_hw); /* Need to read back */
+ if (priv->max_hz >= 62500000)
+ REG_SET(priv->cru_hw, 0x00000006);
+ else if (priv->max_hz >= 50000000)
+ REG_SET(priv->cru_hw, 0x00000002);
+ else if (priv->max_hz >= 31250000)
+ REG_SET(priv->cru_hw, 0x00000004);
+ REG_RD(priv->cru_hw); /* Need to read back */
+
+ /* BSPI: configure for dual/quad mode */
+ if (IPROC_BSPI_DATA_LANES != 1 ||
+ IPROC_BSPI_ADDR_LANES != 1) {
+ /* Disable flex mode first */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 0);
+
+ /* Data / Address lanes */
+ REG_WR(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG, 0);
+ if (IPROC_BSPI_DATA_LANES == 4) {
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ 2 << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
+ } else {
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ (IPROC_BSPI_DATA_LANES - 1)
+ << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
+ }
+ if (IPROC_BSPI_ADDR_LANES == 4) {
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ 2 << BSPI_BITS_PER_CYCLE_ADDR_SHIFT);
+ } else {
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ (IPROC_BSPI_ADDR_LANES - 1)
+ << BSPI_BITS_PER_CYCLE_ADDR_SHIFT);
+ }
+
+ /* Dummy cycles */
+ REG_CLR(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG, 0xFF);
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG,
+ IPROC_BSPI_READ_DUMMY_CYCLES);
+
+ /* Command byte for BSPI */
+ REG_WR(priv->bspi_hw + BSPI_CMD_AND_MODE_BYTE_REG,
+ IPROC_BSPI_READ_CMD);
+
+ /* Enable flex mode to take effect */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 1);
+ }
+
+ /* MSPI: Basic hardware initialization */
+ REG_WR(priv->mspi_hw + MSPI_SPCR1_LSB_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_SPCR1_MSB_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_NEWQP_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_ENDQP_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, 0);
+
+ /* MSPI: SCK configuration */
+ spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
+ REG_WR(priv->mspi_hw + MSPI_SPCR0_LSB_REG,
+ max(min(spbr, SPBR_MAX), SPBR_MIN));
+
+ /* MSPI: Mode configuration (8 bits by default) */
+ priv->mspi_16bit = 0;
+ REG_WR(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
+ 0x80 | /* Master */
+ (8 << 2) | /* 8 bits per word */
+ (priv->spi_mode & 3)); /* mode: CPOL / CPHA */
+
+ return &priv->slave;
+}
+
+void iproc_qspi_free_slave(struct spi_slave *slave)
+{
+ struct bcmspi_priv *priv;
+
+ if (!slave)
+ return;
+ priv = to_qspi_slave(slave);
+ free(priv);
+}
+#endif
+
+#ifdef CONFIG_BCM_IPROC_USE_BSPI
+static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
+{
+ REG_WR(priv->bspi_hw + BSPI_B0_CTRL_REG, 0);
+ REG_WR(priv->bspi_hw + BSPI_B1_CTRL_REG, 0);
+ REG_WR(priv->bspi_hw + BSPI_B0_CTRL_REG, 1);
+ REG_WR(priv->bspi_hw + BSPI_B1_CTRL_REG, 1);
+}
+
+static int bcmspi_enable_bspi(struct bcmspi_priv *priv)
+{
+ if (priv->state == QSPI_STATE_BSPI)
+ return 0;
+
+ /* Disable write lock */
+ REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0);
+
+ /* Flush prefetch buffers */
+ bspi_flush_prefetch_buffers(priv);
+
+ /* Switch to BSPI */
+ REG_WR(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0);
+
+ /* Update state */
+ priv->state = QSPI_STATE_BSPI;
+
+ return 0;
+}
+#endif
+static int bcmspi_disable_bspi(struct bcmspi_priv *priv)
+{
+ if (priv->state == QSPI_STATE_MSPI)
+ return 0;
+
+ /* Switch to MSPI if not yet */
+ if ((REG_RD(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
+ unsigned long start = get_timer(0);
+
+ while (get_timer(start) <
+ QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
+ if ((REG_RD(priv->bspi_hw + BSPI_BUSY_STATUS_REG) & 1)
+ == 0) {
+ REG_WR(priv->bspi_hw +
+ BSPI_MAST_N_BOOT_CTRL_REG, 1);
+ udelay(1);
+ break;
+ }
+ udelay(1);
+ }
+ if ((REG_RD(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & 1)
+ != 1)
+ return -1;
+ }
+
+ /* Update state */
+ priv->state = QSPI_STATE_MSPI;
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+int iproc_qspi_claim_bus(struct spi_slave *slave)
+{
+ struct bcmspi_priv *priv;
+
+ if (!slave)
+ return -1;
+
+ priv = to_qspi_slave(slave);
+ if (priv->state != QSPI_STATE_DISABLED)
+ return 0; /* Already enabled */
+
+#ifndef CONFIG_BCM_IPROC_USE_BSPI
+ /* Switch to MSPI by default */
+ if (bcmspi_disable_bspi(priv) != 0)
+ return -1;
+#else
+ /* Switch to BSPI by default */
+ if (bcmspi_enable_bspi(priv) != 0)
+ return -1;
+#endif
+
+ return 0;
+}
+
+void iproc_qspi_release_bus(struct spi_slave *slave)
+{
+ struct bcmspi_priv *priv;
+
+ if (!slave)
+ return;
+
+ priv = to_qspi_slave(slave);
+ if (priv->state == QSPI_STATE_DISABLED)
+ return;
+
+ /* Make sure no operation is in progress */
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, 0);
+ udelay(1);
+
+#ifndef CONFIG_BCM_IPROC_USE_BSPI
+ /* Switch to MSPI */
+ bcmspi_disable_bspi(priv);
+#else
+ /* Switch to BSPI */
+ bcmspi_enable_bspi(priv);
+#endif
+
+ /* Update state */
+ priv->state = QSPI_STATE_DISABLED;
+}
+#endif
+
+#ifdef CONFIG_BCM_IPROC_USE_BSPI
+static void bspi_set_4byte_mode(struct bcmspi_priv *priv, int enable)
+{
+ /* Disable flex mode first */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 0);
+
+ if (enable) {
+ /* Enable 32-bit address */
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG,
+ BSPI_BITS_PER_PHASE_ADDR_MARK);
+
+ /* Enable flex mode to take effect */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 1);
+ } else {
+ /* Disable 32-bit address */
+ REG_CLR(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG,
+ BSPI_BITS_PER_PHASE_ADDR_MARK);
+
+ /* Clear upper address byte */
+ REG_WR(priv->bspi_hw + BSPI_FLASH_UPPER_ADDR_BYTE_REG, 0);
+
+ /*
+ * Flush prefetch buffers since 32MB window BSPI
+ * could be used
+ */
+ bspi_flush_prefetch_buffers(priv);
+ }
+
+ /* Record current mode */
+ priv->mode_4byte = enable;
+}
+
+#define DWORD_ALIGNED(a) (!(((unsigned long)(a)) & 3))
+
+static void bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
+{
+ u32 status;
+ uint words;
+ int aligned;
+
+ /* Flush data from the previous session (unlikely) */
+ for (;;) {
+ status = REG_RD(priv->bspi_hw_raf + BSPI_RAF_STATUS_REG);
+ if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
+ REG_RD(priv->bspi_hw_raf + BSPI_RAF_READ_DATA_REG);
+ continue;
+ }
+ if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK))
+ break;
+ }
+
+ /* Transfer is in words */
+ words = (bytes + 3) / 4;
+
+ /* Setup hardware */
+ if (priv->mode_4byte) {
+ u32 val = priv->bspi_addr & 0xFF000000;
+
+ if (val != REG_RD(priv->bspi_hw +
+ BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
+ REG_WR(priv->bspi_hw + BSPI_FLASH_UPPER_ADDR_BYTE_REG,
+ val);
+ bspi_flush_prefetch_buffers(priv);
+ }
+ }
+ REG_WR(priv->bspi_hw_raf + BSPI_RAF_START_ADDRESS_REG,
+ priv->bspi_addr & 0x00FFFFFF);
+ REG_WR(priv->bspi_hw_raf + BSPI_RAF_NUM_WORDS_REG, words);
+ REG_WR(priv->bspi_hw_raf + BSPI_RAF_WATERMARK_REG, 0);
+
+ /* Kick off */
+ REG_WR(priv->bspi_hw_raf + BSPI_RAF_CTRL_REG,
+ BSPI_RAF_CONTROL_START_MASK);
+
+ /* Reading the data */
+ aligned = DWORD_ALIGNED(rx);
+ while (bytes) {
+ status = REG_RD(priv->bspi_hw_raf + BSPI_RAF_STATUS_REG);
+ if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
+ u32 data = le32_to_cpu(REG_RD(priv->bspi_hw_raf +
+ BSPI_RAF_READ_DATA_REG));
+
+ /* Check if we can use the whole word */
+ if (aligned && bytes >= 4) {
+ /*
+ * RAF is LE only,
+ * convert data to host endianness
+ */
+ *(u32 *)rx = le32_to_cpu(data);
+ rx += 4;
+ bytes -= 4;
+ } else {
+ uint chunk = min(bytes, 4U);
+
+ /* Read out bytes one by one */
+ while (chunk) {
+ *rx++ = (u8)data;
+ data >>= 8;
+ chunk--;
+ bytes--;
+ }
+ }
+
+ continue;
+ }
+ if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
+ /* FIFO is empty and the session is done */
+ break;
+ }
+ }
+}
+
+static int bspi_emulate_flash_read(struct bcmspi_priv *priv,
+ const u8 *tx, u8 *rx, uint bytes,
+ unsigned long flags)
+{
+ int idx = priv->mode_4byte ? 2 : 1;
+
+ /* Check the address */
+ if (flags & SPI_XFER_BEGIN) {
+ u32 addr;
+
+ /* Drop if the first transfer doesn't contain full address */
+ if (bytes < idx + 3 + 1)
+ return -1;
+
+ /* Flash offset - lower 24 bits */
+ addr = (tx[idx] << 16) | (tx[idx + 1] << 8) | tx[idx + 2];
+
+ /* Flash offset - upper 8 bits */
+ if (priv->mode_4byte)
+ addr |= tx[1] << 24;
+
+ /* Remaining length for data (excluding one dummy cycle) */
+ bytes -= idx + 3 + 1;
+ if (rx)
+ rx += idx + 3 + 1;
+
+ /* non-aligned transfers are handled by MSPI */
+ if (!DWORD_ALIGNED(addr))
+ return -1;
+
+ /* Switch to BSPI */
+ if (bcmspi_enable_bspi(priv) != 0)
+ return -1;
+
+ /* Record BSPI status */
+ priv->bspi_op = OPCODE_FAST_READ;
+ priv->bspi_addr = addr;
+ }
+
+ /* Transfer data if any */
+ while (bytes && rx) {
+ /* Special handing since RAF cannot go across 16MB boundary */
+ uint trans = bytes;
+
+ /*
+ * Divide into multiple transfers if it goes
+ * across the boundary
+ */
+ if (priv->mode_4byte &&
+ (priv->bspi_addr >> 24) !=
+ ((priv->bspi_addr + bytes) >> 24)) {
+ /*
+ * Limit this transfer to not go beyond
+ * 16MB boundary
+ */
+ trans = 0x1000000 - (priv->bspi_addr & 0xFFFFFF);
+ }
+ bspi_read_via_raf(priv, rx, trans);
+ priv->bspi_addr += trans;
+ rx += trans;
+ bytes -= trans;
+ }
+
+ /* Flush prefetch buffers at the end */
+ if (flags & SPI_XFER_END)
+ bspi_flush_prefetch_buffers(priv);
+
+ return 0;
+}
+
+static int bspi_emulate_flash_rdsr(struct bcmspi_priv *priv,
+ const u8 *tx, u8 *rx, uint bytes,
+ unsigned long flags)
+{
+ /* Only emulate the status register if it was a BSPI read */
+ if (priv->state != QSPI_STATE_BSPI)
+ return -1;
+
+ /* Handle for the first transfer */
+ if (flags & SPI_XFER_BEGIN) {
+ /* Record status */
+ priv->bspi_op = OPCODE_RDSR;
+
+ /* Skip the first byte: command */
+ bytes--;
+ rx++;
+ }
+
+ /* Fill the rx data with 0 */
+ while (bytes) {
+ *rx++ = 0x00;
+ bytes--;
+ }
+
+ return 0;
+}
+#endif
+
+static int mspi_xfer(struct bcmspi_priv *priv, uint bytes,
+ const u8 *tx, u8 *rx, unsigned long flags)
+{
+ u32 cdr = CDRAM_PCS0;
+
+ if (flags & SPI_XFER_QUAD) {
+ cdr |= CDRAM_QUAD_MODE;
+
+ if (!tx)
+ cdr |= CDRAM_RBIT_INPUT;
+ }
+ if (bytes & 1) {
+ /* Use 8-bit queue for odd-bytes transfer */
+ if (priv->mspi_16bit) {
+ REG_SET(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
+ MSPI_SPCR0_MSB_BITS_8);
+ priv->mspi_16bit = 0;
+ }
+ } else {
+ /* Use 16-bit queue for even-bytes transfer */
+ if (!priv->mspi_16bit) {
+ REG_CLR(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
+ MSPI_SPCR0_MSB_BITS_8);
+ priv->mspi_16bit = 1;
+ }
+ }
+
+ while (bytes) {
+ uint chunk;
+ uint queues;
+ unsigned long start;
+ uint i;
+
+ /* Separate code for 16bit and 8bit transfers for performance */
+ if (priv->mspi_16bit) {
+ /* Determine how many bytes to process this time */
+ chunk = min(bytes, NUM_CDRAM * 2);
+ queues = (chunk - 1) / 2 + 1;
+ bytes -= chunk;
+
+ /* Fill CDRAMs */
+ for (i = 0; i < queues; i++)
+ REG_WR(priv->mspi_hw + MSPI_CDRAM_REG +
+ (i << 2), cdr | CDRAM_CONT |
+ CDRAM_BITS_EN);
+
+ /* Fill TXRAMs */
+ for (i = 0; i < chunk; i++)
+ REG_WR(priv->mspi_hw + MSPI_TXRAM_REG +
+ (i << 2), tx ? tx[i] : 0xff);
+ } else {
+ /* Determine how many bytes to process this time */
+ chunk = min(bytes, NUM_CDRAM);
+ queues = chunk;
+ bytes -= chunk;
+
+ /* Fill CDRAMs and TXRAMS */
+ for (i = 0; i < chunk; i++) {
+ REG_WR(priv->mspi_hw + MSPI_CDRAM_REG +
+ (i << 2), cdr | CDRAM_CONT);
+ REG_WR(priv->mspi_hw + MSPI_TXRAM_REG +
+ (i << 3), tx ? tx[i] : 0xff);
+ }
+ }
+
+ /* Setup queue pointers */
+ REG_WR(priv->mspi_hw + MSPI_NEWQP_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_ENDQP_REG, queues - 1);
+
+ /* Deassert CS if requested and it's the last transfer */
+ if (bytes == 0 && (flags & SPI_XFER_END))
+ REG_CLR(priv->mspi_hw + MSPI_CDRAM_REG +
+ ((queues - 1) << 2), CDRAM_CONT);
+
+ /* Kick off */
+ REG_WR(priv->mspi_hw + MSPI_STATUS_REG, 0);
+ if (bytes == 0 && (flags & SPI_XFER_END))
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, MSPI_SPE);
+ else
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, MSPI_SPE |
+ MSPI_CONT_AFTER_CMD);
+
+ /* Wait for completion */
+ start = get_timer(0);
+ while (get_timer(start) <
+ QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
+ if (REG_RD(priv->mspi_hw + MSPI_STATUS_REG) & 1)
+ break;
+ }
+ if ((REG_RD(priv->mspi_hw + MSPI_STATUS_REG) & 1) == 0)
+ return -1;
+
+ /* Read data out */
+ if (rx) {
+ if (priv->mspi_16bit) {
+ for (i = 0; i < chunk; i++) {
+ rx[i] = REG_RD(priv->mspi_hw +
+ MSPI_RXRAM_REG +
+ (i << 2))
+ & 0xff;
+ }
+ } else {
+ for (i = 0; i < chunk; i++) {
+ rx[i] = REG_RD(priv->mspi_hw +
+ MSPI_RXRAM_REG +
+ (((i << 1) + 1) << 2))
+ & 0xff;
+ }
+ }
+ }
+
+ /* Advance pointers */
+ if (tx)
+ tx += chunk;
+ if (rx)
+ rx += chunk;
+ }
+
+ return 0;
+}
+
+#ifndef CONFIG_DM_SPI
+int iproc_qspi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct bcmspi_priv *priv;
+ const u8 *tx = dout;
+ u8 *rx = din;
+ uint bytes = bitlen / 8;
+ int ret = 0;
+
+ if (!slave)
+ return -1;
+
+ priv = to_qspi_slave(slave);
+ if (priv->state == QSPI_STATE_DISABLED)
+ return -1;
+
+ /* we can only do 8 bit transfers */
+ if (bitlen % 8)
+ return -1;
+
+#ifdef CONFIG_BCM_IPROC_USE_BSPI
+ /* Check if we can make use of BSPI */
+ if (flags & SPI_XFER_BEGIN) {
+ /* We only use BSPI if the first transfer contains command */
+ if (bytes) {
+ switch (tx[0]) {
+ case OPCODE_FAST_READ:
+ if (bspi_emulate_flash_read
+ (priv, tx, rx, bytes, flags) == 0) {
+ return 0;
+ }
+ break;
+ case OPCODE_RDSR:
+ if (bspi_emulate_flash_rdsr
+ (priv, tx, rx, bytes, flags) == 0) {
+ return 0;
+ }
+ break;
+ case OPCODE_EN4B:
+ bspi_set_4byte_mode(priv, 1);
+ break;
+ case OPCODE_EX4B:
+ bspi_set_4byte_mode(priv, 0);
+ break;
+ case OPCODE_BRWR:
+ bspi_set_4byte_mode(priv, tx[1] ? 1 : 0);
+ break;
+ default:
+ break;
+ }
+ }
+
+ } else if (priv->state == QSPI_STATE_BSPI) {
+ /* It's a following BSPI operation */
+ switch (priv->bspi_op) {
+ case OPCODE_FAST_READ:
+ if (bspi_emulate_flash_read(priv, tx, rx, bytes, flags)
+ == 0)
+ return 0;
+ break;
+ case OPCODE_RDSR:
+ if (bspi_emulate_flash_rdsr(priv, tx, rx, bytes, flags)
+ == 0) {
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ return -1;
+ }
+#endif
+ /* MSPI: Enable write lock at the beginning */
+ if (flags & SPI_XFER_BEGIN) {
+ /* Switch to MSPI if not yet */
+ if (bcmspi_disable_bspi(priv) != 0)
+ return -1;
+
+ REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 1);
+ }
+
+ /* MSPI: Transfer it */
+ if (bytes)
+ ret = mspi_xfer(priv, bytes, tx, rx, flags);
+
+ /* MSPI: Disable write lock if it's done */
+ if (flags & SPI_XFER_END)
+ REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_DM_SPI
+static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
+{
+ struct bcmspi_priv *priv = dev_get_priv(bus);
+ unsigned int spbr;
+
+ priv->max_hz = speed;
+
+ /* MSPI: SCK configuration */
+ spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
+ REG_WR(priv->mspi_hw + MSPI_SPCR0_LSB_REG,
+ max(min(spbr, SPBR_MAX), SPBR_MIN));
+
+ return 0;
+}
+
+static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
+{
+ struct bcmspi_priv *priv = dev_get_priv(bus);
+ u32 data_lanes;
+
+ priv->spi_mode = mode;
+
+ if (mode & SPI_RX_QUAD)
+ data_lanes = 4;
+ else if (mode & SPI_RX_DUAL)
+ data_lanes = 2;
+ else if (mode & SPI_RX_4X)
+ data_lanes = 4;
+ else
+ data_lanes = 1;
+
+ if (data_lanes != 1) {
+ /* BSPI: configure for dual/quad mode */
+ REG_WR(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG, 0);
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 0);
+ /* Dummy cycles */
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG,
+ IPROC_BSPI_READ_DUMMY_CYCLES);
+ /* Override the strap settings */
+ REG_SET(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_SHIFT));
+ /*
+ * Configure following based on QUAD/DUAL mode
+ * - data_quad or data_dual_n_sgl
+ * - data_bpc select
+ * - bspi_cmd_byte
+ */
+ if (data_lanes == 4) {
+ REG_SET(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
+ REG_CLR(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
+
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ 2 << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
+
+ REG_WR(priv->bspi_hw + BSPI_CMD_AND_MODE_BYTE_REG,
+ OPCODE_QUAD_READ);
+ } else if (data_lanes == 2) {
+ REG_CLR(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
+ REG_SET(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
+
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG,
+ 1 << BSPI_BITS_PER_CYCLE_DATA_SHIFT);
+
+ REG_WR(priv->bspi_hw + BSPI_CMD_AND_MODE_BYTE_REG,
+ OPCODE_DUAL_READ);
+ }
+ /* Enable flex mode to take effect */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 1);
+ } else {
+ /* configure BSPI for single mode */
+ REG_WR(priv->bspi_hw + BSPI_FLEX_MODE_ENABLE_REG, 0);
+ REG_WR(priv->bspi_hw + BSPI_BITS_PER_CYCLE_REG, 0);
+ /* Dummy cycles */
+ REG_SET(priv->bspi_hw + BSPI_BITS_PER_PHASE_REG,
+ IPROC_BSPI_READ_DUMMY_CYCLES);
+ /* clear strap override, data_dual_n_sgl and data_quad bits */
+ REG_CLR(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_SHIFT));
+ REG_CLR(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
+ REG_CLR(priv->bspi_hw + BSPI_STRAP_OVERRIDE_CTRL_REG,
+ (1 << BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
+ /* set fast read command */
+ REG_WR(priv->bspi_hw + BSPI_CMD_AND_MODE_BYTE_REG,
+ OPCODE_FAST_READ);
+ }
+
+ /*
+ * MSPI: Mode configuration (8 bits by default)
+ * MSPI supports only single mode.
+ */
+ priv->mspi_16bit = 0;
+ REG_WR(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
+ 0x80 | /* Master */
+ (8 << 2) | /* 8 bits per word */
+ (priv->spi_mode & 3)); /* mode: CPOL / CPHA */
+
+ return 0;
+}
+
+static int iproc_qspi_claim_bus(struct udevice *dev)
+{
+ /* nothing to do */
+ return 0;
+}
+
+static int iproc_qspi_release_bus(struct udevice *dev)
+{
+ struct udevice *bus = dev->parent;
+ struct bcmspi_priv *priv = dev_get_priv(bus);
+
+ /* Make sure no operation is in progress */
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, 0);
+ udelay(1);
+
+ return 0;
+}
+
+static int iproc_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct bcmspi_priv *priv = dev_get_priv(bus);
+ const u8 *tx = dout;
+ u8 *rx = din;
+ uint bytes = bitlen / 8;
+ int ret = 0;
+
+ /* we can only do 8 bit transfers */
+ if (bitlen % 8)
+ return -1;
+
+#ifdef CONFIG_BCM_IPROC_USE_BSPI
+ /* Check if we can make use of BSPI */
+ if (flags & SPI_XFER_BEGIN) {
+ /* We only use BSPI if the first transfer contains command */
+ if (bytes) {
+ switch (tx[0]) {
+ case OPCODE_FAST_READ:
+ case OPCODE_DUAL_READ:
+ case OPCODE_QUAD_READ:
+ if (bspi_emulate_flash_read
+ (priv, tx, rx, bytes, flags) == 0) {
+ return 0;
+ }
+ break;
+ case OPCODE_RDSR:
+ if (bspi_emulate_flash_rdsr
+ (priv, tx, rx, bytes, flags) == 0) {
+ return 0;
+ }
+ break;
+ case OPCODE_EN4B:
+ bspi_set_4byte_mode(priv, 1);
+ break;
+ case OPCODE_EX4B:
+ bspi_set_4byte_mode(priv, 0);
+ break;
+ case OPCODE_BRWR:
+ bspi_set_4byte_mode(priv, tx[1] ? 1 : 0);
+ break;
+ default:
+ break;
+ }
+ }
+
+ } else if (priv->state == QSPI_STATE_BSPI) {
+ /* It's a following BSPI operation */
+ switch (priv->bspi_op) {
+ case OPCODE_FAST_READ:
+ case OPCODE_DUAL_READ:
+ case OPCODE_QUAD_READ:
+ if (bspi_emulate_flash_read(priv, tx, rx, bytes, flags)
+ == 0)
+ return 0;
+ break;
+ case OPCODE_RDSR:
+ if (bspi_emulate_flash_rdsr(priv, tx, rx, bytes, flags)
+ == 0) {
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+ return -1;
+ }
+#endif
+
+ /* MSPI: Enable write lock at the beginning */
+ if (flags & SPI_XFER_BEGIN) {
+ /* Switch to MSPI if not yet */
+ if (bcmspi_disable_bspi(priv) != 0)
+ return -1;
+
+ REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 1);
+ }
+
+ /* MSPI: Transfer it */
+ if (bytes)
+ ret = mspi_xfer(priv, bytes, tx, rx, flags);
+
+ /* MSPI: Disable write lock if it's done */
+ if (flags & SPI_XFER_END) {
+ REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0);
+#ifdef CONFIG_BCM_IPROC_USE_BSPI
+ /* Switch to back to BSPI */
+ REG_WR(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0);
+#endif
+ }
+
+ return ret;
+}
+
+static int iproc_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct bcmspi_platdata *plat = bus->platdata;
+ ofnode subnode;
+
+ plat->bspi_hw = (void __iomem *)devfdt_get_addr_name(bus, "bspi");
+ if (IS_ERR(plat->bspi_hw)) {
+ debug("Error: can't get regs base addresses\n");
+ return PTR_ERR(plat->bspi_hw);
+ }
+
+ plat->bspi_hw_raf =
+ (void __iomem *)devfdt_get_addr_name(bus, "bspi_raf");
+ if (IS_ERR(plat->bspi_hw_raf)) {
+ debug("Error: can't get regs base addresses\n");
+ return PTR_ERR(plat->bspi_hw_raf);
+ }
+
+ plat->mspi_hw = (void __iomem *)devfdt_get_addr_name(bus, "mspi");
+ if (IS_ERR(plat->mspi_hw)) {
+ debug("Error: can't get regs base addresses\n");
+ return PTR_ERR(plat->mspi_hw);
+ }
+
+ subnode = dev_read_first_subnode(bus);
+ if (ofnode_valid(subnode))
+ plat->frequency = ofnode_read_u32_default(subnode,
+ "spi-max-frequency",
+ QSPI_DEF_SCK_FREQ);
+ else
+ plat->frequency = QSPI_DEF_SCK_FREQ;
+
+ return 0;
+}
+
+static int iproc_qspi_probe(struct udevice *bus)
+{
+ struct bcmspi_priv *priv = dev_get_priv(bus);
+ struct bcmspi_platdata *plat = dev_get_platdata(bus);
+
+ priv->mode_4byte = 0;
+ priv->bspi_hw = plat->bspi_hw;
+ priv->bspi_hw_raf = plat->bspi_hw_raf;
+ priv->mspi_hw = plat->mspi_hw;
+ priv->max_hz = plat->frequency;
+
+ /* MSPI: Basic hardware initialization */
+ REG_WR(priv->mspi_hw + MSPI_SPCR1_LSB_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_SPCR1_MSB_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_NEWQP_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_ENDQP_REG, 0);
+ REG_WR(priv->mspi_hw + MSPI_SPCR2_REG, 0);
+
+#ifndef CONFIG_BCM_IPROC_USE_BSPI
+ if (bcmspi_disable_bspi(priv) != 0) {
+ printf("Failed to set in MSPI mode\n");
+ return -1;
+ }
+#else
+ if (bcmspi_enable_bspi(priv) != 0) {
+ printf("Failed to set in BSPI mode\n");
+ return -1;
+ }
+#endif
+
+ return 0;
+}
+
+static const struct dm_spi_ops iproc_qspi_ops = {
+ .claim_bus = iproc_qspi_claim_bus,
+ .release_bus = iproc_qspi_release_bus,
+ .xfer = iproc_qspi_xfer,
+ .set_speed = iproc_qspi_set_speed,
+ .set_mode = iproc_qspi_set_mode,
+};
+
+static const struct udevice_id iproc_qspi_ids[] = {
+ { .compatible = "brcm,iproc-qspi" },
+ { }
+};
+
+U_BOOT_DRIVER(iproc_qspi) = {
+ .name = "iproc_qspi",
+ .id = UCLASS_SPI,
+ .of_match = iproc_qspi_ids,
+ .ops = &iproc_qspi_ops,
+ .ofdata_to_platdata = iproc_qspi_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct bcmspi_platdata),
+ .priv_auto_alloc_size = sizeof(struct bcmspi_priv),
+ .probe = iproc_qspi_probe,
+};
+#endif
diff --git a/drivers/spi/iproc_qspi.h b/drivers/spi/iproc_qspi.h
new file mode 100644
index 0000000000..3d2f5ee944
--- /dev/null
+++ b/drivers/spi/iproc_qspi.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Broadcom.
+ */
+
+#include <spi.h>
+
+#ifndef _IPROC_QSPI_H_
+#define _IPROC_QSPI_H_
+
+/*SPI configuration enable*/
+#define IPROC_QSPI_BUS 0
+#define IPROC_QSPI_CS 0
+
+#ifdef CONFIG_TARGET_BCMOMEGA
+#define IPROC_QSPI_BASE_REG 0x288d0000
+#define IPROC_QSPI_CRU_CONTROL_REG 0x285b0280
+#define IPROC_BSPI_DATA_LANES 1
+#define IPROC_BSPI_ADDR_LANES 1
+#else
+#define IPROC_QSPI_BASE_REG 0x18047000
+#define IPROC_QSPI_CRU_CONTROL_REG 0x1800e000
+#define IPROC_BSPI_DATA_LANES 1
+#define IPROC_BSPI_ADDR_LANES 1
+#endif
+
+#ifndef CONFIG_DM_SPI
+int iproc_qspi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+struct spi_slave *iproc_qspi_setup_slave(unsigned int bus,
+ unsigned int cs,
+ unsigned int max_hz,
+ unsigned int mode);
+
+void iproc_qspi_free_slave(struct spi_slave *slave);
+
+int iproc_qspi_claim_bus(struct spi_slave *slave);
+
+void iproc_qspi_release_bus(struct spi_slave *slave);
+
+int iproc_qspi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *dout, void *din, unsigned long flags);
+#endif
+
+#define IPROC_BSPI_READ_CMD 0x0b
+#define IPROC_BSPI_READ_DUMMY_CYCLES 0x08
+#endif /* _IPROC_QSPI_H_ */
diff --git a/drivers/spi/iproc_spi.c b/drivers/spi/iproc_spi.c
new file mode 100644
index 0000000000..11f49374a1
--- /dev/null
+++ b/drivers/spi/iproc_spi.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 Broadcom.
+ */
+
+#include <common.h>
+#include <spi.h>
+#include "iproc_qspi.h"
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (bus == IPROC_QSPI_BUS)
+ return iproc_qspi_cs_is_valid(bus, cs);
+#endif
+
+ return 0;
+}
+
+void spi_init(void)
+{
+ /* Do nothing */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (bus == IPROC_QSPI_BUS)
+ return iproc_qspi_setup_slave(bus, cs, max_hz, mode);
+#endif
+
+ return NULL;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (slave->bus == IPROC_QSPI_BUS)
+ iproc_qspi_free_slave(slave);
+#endif
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (slave->bus == IPROC_QSPI_BUS)
+ return iproc_qspi_claim_bus(slave);
+#endif
+
+ return -1;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (slave->bus == IPROC_QSPI_BUS)
+ iproc_qspi_release_bus(slave);
+#endif
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+#ifdef CONFIG_IPROC_QSPI
+ if (slave->bus == IPROC_QSPI_BUS)
+ return iproc_qspi_xfer(slave, bitlen, dout, din, flags);
+#endif
+
+ return -1;
+}
--
2.17.1
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