On Wed, Dec 4, 2019 at 4:23 AM Xiaowei Bao <[email protected]> wrote: > > > > > -----Original Message----- > > From: Ramon Fried <[email protected]> > > Sent: 2019年12月4日 4:01 > > To: Xiaowei Bao <[email protected]> > > Cc: Ramon Fried <[email protected]>; Hongbo Wang > > <[email protected]>; [email protected]; York Sun > > <[email protected]>; Z.q. Hou <[email protected]>; Mingkai Hu > > <[email protected]> > > Subject: Re: [U-Boot] [EXT] Re: [PATCHv2 1/2] PCI: layerscape: Add Support > > for ls2088 PCIe EP mode > > > > On Tue, Dec 3, 2019 at 4:32 AM Xiaowei Bao <[email protected]> wrote: > > > > > > Hi Ramon, > > > > > > Do you have any comments about this? Thanks a lot. > > > > > > Best regards > > > Xiaowei > > > > > > From: Xiaowei Bao > > > Sent: 2019年11月26日 10:52 > > > To: Ramon Fried <[email protected]> > > > Cc: Bin Meng <[email protected]>; Simon Glass <[email protected]>; > > > M.h. Lian <[email protected]>; Z.q. Hou <[email protected]>; > > > Mingkai Hu <[email protected]>; Hongbo Wang > > <[email protected]>; > > > York Sun <[email protected]>; [email protected] > > > Subject: RE: [EXT] Re: [U-Boot] [PATCHv2 1/2] PCI: layerscape: Add > > > Support for ls2088 PCIe EP mode > > > > > > H Ramon, > > > > > > Thanks for your comments. > > > If we reimplement the PCIe EP driver base on PCIe UCLASS, we must test it > > in u-boot, but I have no idea how to test the actual device, do I need to > > implement our own test case, how to verify the cadence-ep actual device? > > > > > I'm not sure I understand what you're trying to achieve and why you're > > referring to the cadence. > > You're developing a driver, just test it against a client (IE. a real PCIe > > root-complex). > > The cadence is irrelevant, it's just another implementation of endpoint > > driver. > > Thanks for your comments, do you mean that we can use the 'pci' and 'md' > command > of u-boot to test the EP device when the controller which work as a EP device > connect > to a RC port, we can access the BAR base on the "pci header" command, yes? > but if I want > to test memory access from EP to RC, what should I do, because there is not a > command > which similar to 'pci' to test. > No, I don't mean that. Currently there's no cmd line interface for PCIe endpoint (patches welcome). You should test the driver against a *real* setup, where you configure the endpoint using some init function in the board startup sequence.
> Another issue is that, due to the history reason of Layerscape PCIe > controller driver, the > EP and RC codes are combined, if I separate the EP and RC code, there will > have many > duplicate code. So create a common.c file for both of them. > > Thanks > Xiaowei > > > > > Thanks, > > Ramon. > > > Best regards > > > Xiaowei > > > [email protected] > > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > > > > > s.denx.de%2Flistinfo%2Fu-boot&data=02%7C01%7Cxiaowei.bao%40nxp > > .com > > > %7Cad7a366db91f4e40273308d7782b7fc8%7C686ea1d3bc2b4c6fa92cd99 > > c5c301635 > > > %7C0%7C0%7C637110000532938430&sdata=T0D3QR5RzdFv96syOlG > > VK7OEBQyNdl > > > 8M9pfd%2F4vxOIg%3D&reserved=0
