Add DT nodes related to DMA and CPSW to -u-boot.dtsi to get networking
up on J721e EVM.

Signed-off-by: Vignesh Raghavendra <vigne...@ti.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
Reviewed-by: Grygorii Strashko <grygorii.stras...@ti.com>
---
 .../k3-j721e-common-proc-board-u-boot.dtsi    | 238 ++++++++++++++++++
 1 file changed, 238 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi 
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 541da22c4889..9291e57e258a 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -3,11 +3,18 @@
  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  */
 
+#include <dt-bindings/dma/k3-udma.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
 / {
        chosen {
                stdout-path = "serial2:115200n8";
                tick-timer = &timer1;
        };
+
+       aliases {
+               ethernet0 = &cpsw_port1;
+       };
 };
 
 &cbass_main{
@@ -24,6 +31,184 @@
                clock-frequency = <25000000>;
                u-boot,dm-spl;
        };
+
+       mcu_conf: scm_conf@40f00000 {
+               compatible = "syscon", "simple-mfd";
+               reg = <0x0 0x40f00000 0x0 0x20000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+               phy_sel: cpsw-phy-sel@4040 {
+                       compatible = "ti,am654-cpsw-phy-sel";
+                       reg = <0x4040 0x4>;
+                       reg-names = "gmii-sel";
+               };
+       };
+
+       cbass_mcu_navss: mcu_navss {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-coherent;
+               dma-ranges;
+               ranges;
+
+               ti,sci-dev-id = <232>;
+               u-boot,dm-spl;
+
+               mcu_ringacc: ringacc@2b800000 {
+                       compatible = "ti,am654-navss-ringacc";
+                       reg =   <0x0 0x2b800000 0x0 0x400000>,
+                               <0x0 0x2b000000 0x0 0x400000>,
+                               <0x0 0x28590000 0x0 0x100>,
+                               <0x0 0x2a500000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       ti,num-rings = <286>;
+                       ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <235>;
+                       u-boot,dm-spl;
+               };
+
+               mcu_udmap: udmap@31150000 {
+                       compatible = "ti,j721e-navss-mcu-udmap";
+                       reg =   <0x0 0x285c0000 0x0 0x100>,
+                               <0x0 0x2a800000 0x0 0x40000>,
+                               <0x0 0x2aa00000 0x0 0x40000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt";
+                       #dma-cells = <3>;
+
+                       ti,ringacc = <&mcu_ringacc>;
+                       ti,psil-base = <0x6000>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <236>;
+
+                       ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+                                               <0x0f>; /* TX_HCHAN */
+                       ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+                                               <0x0b>; /* RX_HCHAN */
+                       ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+                       u-boot,dm-spl;
+               };
+       };
+
+       mcu_cpsw: ethernet@046000000 {
+               compatible = "ti,j721e-cpsw-nuss";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               reg = <0x0 0x46000000 0x0 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges;
+               dma-coherent;
+               clocks = <&k3_clks 18 22>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+               ti,psil-base = <0x7000>;
+               cpsw-phy-sel = <&phy_sel>;
+
+               dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
+                      <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
+               dma-names = "tx0", "tx1", "tx2", "tx3",
+                           "tx4", "tx5", "tx6", "tx7",
+                           "rx";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       host: host@0 {
+                               reg = <0>;
+                               ti,label = "host";
+                       };
+
+                       cpsw_port1: port@1 {
+                               reg = <1>;
+                               ti,mac-only;
+                               ti,label = "port1";
+                               ti,syscon-efuse = <&mcu_conf 0x200>;
+                       };
+               };
+
+               davinci_mdio: mdio {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       bus_freq = <1000000>;
+               };
+
+               cpts {
+                       clocks = <&k3_clks 18 2>;
+                       clock-names = "cpts";
+                       interrupts-extended = <&gic500 GIC_SPI 858 
IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cpts";
+                       ti,cpts-ext-ts-inputs = <4>;
+                       ti,cpts-periodic-outputs = <2>;
+               };
+
+               ti,psil-config0 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config1 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config2 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config3 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config4 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config5 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config6 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+
+               ti,psil-config7 {
+                       linux,udma-mode = <UDMA_PKT_MODE>;
+                       statictr-type = <PSIL_STATIC_TR_NONE>;
+                       ti,needs-epib;
+                       ti,psd-size = <16>;
+               };
+       };
 };
 
 &secure_proxy_main {
@@ -52,6 +237,29 @@
 
 &wkup_pmx0 {
        u-boot,dm-spl;
+       mcu_cpsw_pins_default: mcu_cpsw_pins_default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) 
MCU_RGMII1_TX_CTL */
+                       J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) 
MCU_RGMII1_RX_CTL */
+                       J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) 
MCU_RGMII1_TD3 */
+                       J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) 
MCU_RGMII1_TD2 */
+                       J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) 
MCU_RGMII1_TD1 */
+                       J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) 
MCU_RGMII1_TD0 */
+                       J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) 
MCU_RGMII1_RD3 */
+                       J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) 
MCU_RGMII1_RD2 */
+                       J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) 
MCU_RGMII1_RD1 */
+                       J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) 
MCU_RGMII1_RD0 */
+                       J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) 
MCU_RGMII1_TXC */
+                       J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) 
MCU_RGMII1_RXC */
+               >;
+       };
+
+       mcu_mdio_pins_default: mcu_mdio1_pins_default {
+               pinctrl-single,pins = <
+                       J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) 
MCU_MDIO0_MDC */
+                       J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) 
MCU_MDIO0_MDIO */
+               >;
+       };
 };
 
 &main_pmx0 {
@@ -73,3 +281,33 @@
 &main_sdhci1 {
        u-boot,dm-spl;
 };
+
+&mcu_cpsw {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+       phy0: ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+};
+
+&cpsw_port1 {
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&phy0>;
+};
+
+&mcu_cpsw {
+       reg = <0x0 0x46000000 0x0 0x200000>,
+             <0x0 0x40f00200 0x0 0x2>;
+       reg-names = "cpsw_nuss", "mac_efuse";
+
+       cpsw-phy-sel@40f04040 {
+               compatible = "ti,am654-cpsw-phy-sel";
+               reg= <0x0 0x40f04040 0x0 0x4>;
+               reg-names = "gmii-sel";
+       };
+};
-- 
2.24.0

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