On Mon, Dec 02, 2019 at 04:34:21PM -0600, Suman Anna wrote:
> The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
> frequencies based on OPP") added the core logic to update the kernel
> device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
> a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
> family of SoCs.
>
> The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
> provide a higher performance and can run at a higher clock frequency
> of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
> correct clock rates on these SoCs. Note that this higher clock rate is
> not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
> AM574x SoCs) that follow the ABZ package.
>
> Signed-off-by: Suman Anna <[email protected]>
> Reviewed-by: Lokesh Vutla <[email protected]>Applied to u-boot/master, thanks! -- Tom
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