On 1/10/20 7:31 AM, Stefan Roese wrote: > Hi Mauro, > > On 09.01.20 18:28, Mauro Condarelli wrote: >> I managed to brick my target. >> >> Situation: >> I have a board with a paleolithic (1.1.3) version of u-boot. >> I had been testing by loading in ram from USB: >> usb reset; fatload usb 0 80010000 u-boot.bin; go 80010000 >> and everything was ok. >> I changed a few settings (both defconfigs are attached below) >> and tried "the real thing" >> Unfortunately reflashing the actual boot produced a brick. >> It does not utter a single byte. > > Ugh. Too bad. I know... :( >> I will have to reflash the original using an external apparatus >> (which I don't have here, so I'll have to take target to another >> location, probably tomorrow morning), but question is: >> how do I debug such a situation? > > To debug very early problems, I suggest to use the DEBUG_UART interface > in U-Boot. I also used it quite a lot before - also on this platform. > > Please see: > > include/debug_uart.h: > > debug_uart_init(); > printhex8(0x01); > ... > > When using UART2 on the MT7628 please make sure to configure the pin > mux before using the debug uart. Otherwise nothing will get printed. I do *not* do anything explicitly in my code, but I have stanzas in .dts Is that supposed to be enough? (I attach my current .dts as I'm sorry to say I don't really fully grok .dts and I'm merely copying stanzas around).
I have Your code in board/vocore/vocore2/board.c (attached), shouldn't that be enough? > BTW: This might also be a problem on your board, if you use UART2 and > the muxing is not done no output will occur. I understand (see above). >> What could I have done so wrong? >> >> As You can see I changed only a few settings: >> >> --- configs/vocore_vocore2-ram_defconfig 2020-01-09 >> 16:11:12.568096050 +0100 >> +++ configs/vocore_vocore2_defconfig 2020-01-09 16:07:10.528267378 >> +0100 >> @@ -1,9 +1,12 @@ >> CONFIG_MIPS=y >> -CONFIG_SYS_TEXT_BASE=0x80010000 >> +CONFIG_SYS_TEXT_BASE=0x9c000000 >> CONFIG_ENV_SIZE=0x00001000 >> CONFIG_NR_DRAM_BANKS=1 >> CONFIG_ARCH_MTMIPS=y >> CONFIG_BOARD_VOCORE2=y >> +CONFIG_BOOT_ROM=y >> +CONFIG_ONBOARD_DDR2_SIZE_1024MBIT=y >> +CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT=y >> CONFIG_MIPS_BOOT_FDT=y >> CONFIG_ENV_VARS_UBOOT_CONFIG=y >> CONFIG_SYS_BOOT_GET_CMDLINE=y >> ... in a way that's very similar to boards based on the same SoC >> (linkit-smart-7688 and gardena-smart-gateway-mt7688). >> >> In the ancient u-boot I had to remove a header from the RAM >> version, but this was not needed with current u-boot. >> >> Did I forget some step? > > Did you never program U-Boot into SPI NOR before on your VoCore2? Yes. Up to now I've been using the RAM-version and loaded it from my old (paleolithic 1.1.3) vendor-provided u-boot. Note: I have modified and reflashed *that* u-boot several times, so I was kind of confident I could do without much problem. Of course it's fully possible some initialization done by old code is missing in the new one. > Which binary did you program? I flashed "u-boot.bin" which looks like a copy of "u-boot-dtb.bin"; this is exactly the same file I used for my RAM-based tests (after switching _defconfig and recompiling, of course). > How do the fist line look like? Here my output: > > $ hexdump -n 256 u-boot.bin > 0000000 013f 1000 4800 4080 0000 0000 0000 0000 > 0000010 0000 0000 0000 0000 0000 0000 0000 0000 > * > 0000100 Mine is quite similar: $ hexdump -n 256 u-boot.bin 0000000 013f 1000 4800 4080 0000 0000 0000 0000 0000010 0000 0000 0000 0000 0000 0000 0000 0000 * 0000100 I'm about to go where there's a nailbed to reflash SPI NOR "from outside"; I plan to read back what's on flash before putting back the "old" u-boot to see if something went wrong while flashing (but I doubt it). Problem is how to proceed. Old code did a lot of hard-coded initialization (non-DT-based) which I don't (explicitly) do here (including a long RAM calibration I didn't even try to understand). I will bring back a certain number of working modules, so I will have a certain number of "tries" before I need to go back for hard reflashing; I should try to minimize commuting ;) > Thanks, > Stefan Many Thanks Mauro
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/mt7628-clk.h>
#include <dt-bindings/reset/mt7628-reset.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ralink,mt7628a-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "mti,mips24KEc";
device_type = "cpu";
reg = <0>;
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
compatible = "mti,cpu-interrupt-controller";
};
clk48m: clk48m@0 {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
palmbus@10000000 {
compatible = "palmbus", "simple-bus";
reg = <0x10000000 0x200000>;
ranges = <0x0 0x10000000 0x1FFFFF>;
#address-cells = <1>;
#size-cells = <1>;
sysc: system-controller@0 {
compatible = "ralink,mt7620a-sysc", "syscon";
reg = <0x0 0x100>;
};
syscon-reboot {
compatible = "syscon-reboot";
regmap = <&sysc>;
offset = <0x34>;
mask = <0x1>;
};
clkctrl: clkctrl@0x2c {
reg = <0x2c 0x8>, <0x10 0x4>;
reg-names = "syscfg0", "clkcfg";
compatible = "mediatek,mt7628-clk";
#clock-cells = <1>;
u-boot,dm-pre-reloc;
};
clkgate: clkgate@0x30 {
reg = <0x30 0x4>;
compatible = "mediatek,mtmips-clk-gate";
#clock-cells = <1>;
};
rstctrl: rstctrl@0x34 {
reg = <0x34 0x4>;
compatible = "mediatek,mtmips-reset";
#reset-cells = <1>;
};
pinctrl: pinctrl@60 {
compatible = "mediatek,mt7628-pinctrl";
reg = <0x3c 0x2c>, <0x1300 0x100>;
reg-names = "gpiomode", "padconf";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pin_state {
};
spi_single_pins: spi_single_pins {
groups = "spi";
function = "spi";
};
spi_dual_pins: spi_dual_pins {
spi_master_pins {
groups = "spi";
function = "spi";
};
spi_cs1_pin {
groups = "spi cs1";
function = "spi cs1";
};
};
uart0_pins: uart0_pins {
groups = "uart0";
function = "uart0";
};
uart1_pins: uart1_pins {
groups = "uart1";
function = "uart1";
};
uart2_pins: uart2_pins {
groups = "uart2";
function = "uart2";
};
i2c_pins: i2c_pins {
groups = "i2c";
function = "i2c";
};
ephy_iot_mode: ephy_iot_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
ephy0_en {
groups = "ephy0";
function = "enable";
};
};
ephy_router_mode: ephy_router_mode {
ephy4_1_en {
groups = "ephy4_1_pad";
function = "analog";
};
ephy0_en {
groups = "ephy0";
function = "enable";
};
};
sd_iot_mode: sd_iot_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
sdxc_en {
groups = "sdmode";
function = "sdxc";
};
sdxc_iot_mode {
groups = "sd router";
function = "iot";
};
sd_clk_pad {
pins = "sd_clk";
drive-strength-4g = <8>;
};
};
sd_router_mode: sd_router_mode {
sdxc_router_mode {
groups = "sd router";
function = "router";
};
sdxc_map_pins {
groups = "gpio0", "i2s", "sdmode", \
"i2c", "uart1";
function = "gpio";
};
sd_clk_pad {
pins = "gpio0";
drive-strength-28 = <8>;
};
};
emmc_iot_8bit_mode: emmc_iot_8bit_mode {
ephy4_1_dis {
groups = "ephy4_1_pad";
function = "digital";
};
emmc_en {
groups = "sdmode";
function = "sdxc";
};
emmc_iot_mode {
groups = "sd router";
function = "iot";
};
emmc_d4_d5 {
groups = "uart2";
function = "sdxc d5 d4";
};
emmc_d6 {
groups = "pwm1";
function = "sdxc d6";
};
emmc_d7 {
groups = "pwm0";
function = "sdxc d7";
};
sd_clk_pad {
pins = "sd_clk";
drive-strength-4g = <8>;
};
};
};
watchdog: watchdog@100 {
compatible = "ralink,mt7628a-wdt",
"mediatek,mt7621-wdt";
reg = <0x100 0x30>;
resets = <&rstctrl MT7628_TIMER_RST>;
reset-names = "wdt";
interrupt-parent = <&intc>;
interrupts = <24>;
};
intc: interrupt-controller@200 {
compatible = "ralink,rt2880-intc";
reg = <0x200 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
resets = <&rstctrl MT7628_INT_RST>;
reset-names = "intc";
interrupt-parent = <&cpuintc>;
interrupts = <2>;
ralink,intc-registers = <0x9c 0xa0
0x6c 0xa4
0x80 0x78>;
};
memory-controller@300 {
compatible = "ralink,mt7620a-memc";
reg = <0x300 0x100>;
};
gpio@600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
reg = <0x600 0x100>;
resets = <&rstctrl MT7628_PIO_RST>;
reset-names = "pio";
interrupt-parent = <&intc>;
interrupts = <6>;
gpio0: bank@0 {
reg = <0>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
gpio1: bank@1 {
reg = <1>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
gpio2: bank@2 {
reg = <2>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
};
spi0: spi@b00 {
compatible = "ralink,mt7621-spi";
reg = <0xb00 0x40>;
resets = <&rstctrl MT7628_SPI_RST>;
reset-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkctrl CLK_SPI>;
};
uart0: uartlite@c00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xc00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
clocks = <&clkctrl CLK_UART0>;
resets = <&rstctrl MT7628_UART0_RST>;
reset-names = "uart0";
interrupt-parent = <&intc>;
interrupts = <20>;
reg-shift = <2>;
};
uart1: uart1@d00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xd00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
clocks = <&clkctrl CLK_UART1>;
resets = <&rstctrl MT7628_UART1_RST>;
reset-names = "uart1";
interrupt-parent = <&intc>;
interrupts = <21>;
reg-shift = <2>;
};
uart2: uart2@e00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0xe00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
clocks = <&clkctrl CLK_UART2>;
resets = <&rstctrl MT7628_UART2_RST>;
reset-names = "uart2";
interrupt-parent = <&intc>;
interrupts = <22>;
reg-shift = <2>;
};
};
eth: eth@10110000 {
compatible = "mediatek,mt7628-eth";
reg = <0x10100000 0x10000
0x10110000 0x8000>;
resets = <&rstctrl MT7628_EPHY_RST>;
reset-names = "ephy";
syscon = <&sysc>;
};
usb_phy: usb-phy@10120000 {
compatible = "mediatek,mt7628-usbphy";
reg = <0x10120000 0x1000>;
#phy-cells = <0>;
ralink,sysctl = <&sysc>;
resets = <&rstctrl MT7628_UPHY_RST>;
reset-names = "phy";
clocks = <&clkctrl CLK_UPHY>;
clock-names = "cg";
};
ehci@101c0000 {
compatible = "generic-ehci";
reg = <0x101c0000 0x1000>;
phys = <&usb_phy>;
phy-names = "usb";
interrupt-parent = <&intc>;
interrupts = <18>;
};
mmc: mmc@10130000 {
compatible = "mediatek,mt7620-mmc";
reg = <0x10130000 0x4000>;
builtin-cd = <1>;
r_smpl = <1>;
interrupt-parent = <&intc>;
interrupts = <14>;
clocks = <&clk48m>, <&clk48m>;
clock-names = "source", "hclk";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd_iot_mode>;
pinctrl-1 = <&sd_iot_mode>;
vmmc-supply = <&clk48m>;
vqmmc-supply = <&clk48m>;
resets = <&rstctrl MT7628_SDXC_RST>;
status = "disabled";
};
};
vocore_vocore2.dts
Description: audio/vnd.dts
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Mauro Condarelli <mc5...@mclink.it>
*
* Note: this is largely copied from:
* board/seeed/linkit_smart_7688/board.c
* Copyright (C) 2018 Stefan Roese <s...@denx.de>
*/
#include <common.h>
#include <asm/io.h>
#define MT76XX_GPIO1_MODE 0x10000060
DECLARE_GLOBAL_DATA_PTR;
void board_debug_uart_init(void)
{
void __iomem *gpio_mode;
/* Select UART2 mode instead of GPIO mode (default) */
gpio_mode = ioremap_nocache(MT76XX_GPIO1_MODE, 0x100);
clrbits_le32(gpio_mode, GENMASK(27, 26));
}
int board_early_init_f(void)
{
/*
* The pin muxing of UART2 also needs to be done, if debug uart
* is not enabled. So we need to call this function here as well.
*/
board_debug_uart_init();
return 0;
}
