Hi Mauro,
On 15.01.20 11:23, Mauro Condarelli wrote:
I am surprised though as all I could find on differences between
MT7628 and MT7688 are is a reference on Mediatek site:
https://docs.labs.mediatek.com/resource/linkit-smart-7688/en/faq
Q: What’s MT7628 and how is it different from MT7688AN?
The MT7628 series are pin-to-pin compatible with the MT7688 series.
However, MT7628 comes with a 2T2R antenna, while MT7688 only supports
1T1R antenna.
(Incomplete!) comparison of the two datasheets did not show
relevant differences.
I have started an analysis of current register status (and I quickly hit
limitation of the documentation I have):
b0000008: 00010000 ....
E-Fuse Configuration is not pristine, but I don't know what it my mean.
b0000010: 00111144 D...
System Configuration Register 0 ->0000 0000 0001 0001 0001 0001 1000 1000
Not correct:
System Configuration Register 0 ->0000 0000 0001 0001 0001 0001 0100 0100
00000000 TEST_CODE
000 *
100010001 BS_SHADOW
000 *
1 DBG_JTAG_MODE 1: Normal Boot-up
1 TEST_MODE_1 ??
0 XTAL_FREQ_SEL 0: 25MHz DIP ???
0 EXT_BG 0: BG clock from PMU
0 TEST_MODE_0 0: SUTIF
100 CHIP_MODE 100: SCAN mode
Not correct. You have here 010, so XTAL with 3-byte ADR
0 DRAM_TYPE 0: DDR2
I am concerned by TEST_MODE_1,XTAL_FREQ_SEL and CHIP_MODE that might
signal a different up/down pulling of Bootstrapping Pins.
Could You cross check on LinkIt, please?
=> md b0000000
b0000000: 3637544d 20203832 00100000 00010102 MT7628 ........
b0000010: 00156156 02605500 00000000 00000000 Va...U`.........
b0000020: 10240000 00000000 00000071 0020100c ..$.....q..... .
b0000030: ffffffc0 04000000 c0030004 00fe00ff ................
b0000040: 00000000 0001ffff 00000000 00000000 ................
b0000050: 00000000 00000000 00000000 00000810 ................
b0000060: 50050404 05550551 00000000 00000000 ...PQ.U.........
SYSCFG0: 00156156
CHIP_MODE: 011: XTAL with 4-byte ADR.
Mainline U-Boot reports this:
CPU: MT7628 Rev 1.2 - Boot from XTAL (4-Byte SPI Addr)
and the new code from Weijie reports this:
CPU: MediaTek MT7688A ver:1 eco:2
Boot: DDR2, SPI-NOR 4-Byte Addr, CPU clock from XTAL
Clock: CPU: 580MHz, Bus: 193MHz, XTAL: 40MHz
One important difference which might explain a lot, it XTAL_FREQ_SEL
which is 0 in your case and 1 in my case.
IIUTC, then the new code from Weijie takes this XTAL selection
into account. Weijie might comment on this. I suggest that you give
this "u-boot-mtmips.bin" binary a try. Good luck. :)
Thanks,
Stefan
