Hi
On Wed., 15 Jan. 2020, 1:56 pm Stefano Babic, <[email protected]> wrote: > Hi Michael, > > your patch is huge.... > > Let's agree. One patch without eeprom support and minimal things Add eeprom support and board detect Add other memory configuration Micahel On 12/01/20 14:08, Michael Trimarchi wrote: > > > https://www.avnet.com/wps/portal/integrated/products/embedded-boards/smarc-modules/ > > > > - Single, Dual or Quad core ARM Cortex-A53 Applications Processor up to > 1.8GHz > > - ARM Cortex-M4 Real Time Processor at 400MHz > > - Vivante GC NanoUltra 2D/3D Graphics Processor > > 1080p60 H.265 decode, 1080p60 H.264 encode (VPU not available on ”Mini > Lite“) > > - Up to 4GB LPDDR4 SDRAM > > - Up to 64GB eMMC Flash > > - Dual-channel LVDS / Dual MIPI-DSI x4 (optional) > > - MIPI CSI-2 Camera Interface > > - PCI Express x1 Gen. 2 > > > > - 4x USB 2.0 Host interface > > - 1x USB 2.0 Host/Device interface > > - Gigabit Ethernet > > - Wireless Module (optional) > > - Micro SD Card Socket (optional) > > - MMC/SD/SDIO interface > > - 2x CAN interface (optional) > > - 2x I2S Audio Interface > > - UART, SPI, I2C > > - SMARC 2.0 Compliant > > > > Peripheral supported in bootloader > > > > - console uart1 > > - mmc > > - emmc > > - eeprom and memory configuration according to the specific one > > - create fdt_file compatible with msc/avnet yocto distribuition > > > > Signed-off-by: Waldemar Glensk <[email protected]> > > Signed-off-by: Michael Trimarchi <[email protected]> > > --- > > Changes: v1->v2: > > change size does not fit mailing list. Remove > > some memory configuration can not be tested in this > > reference module > > > > --- > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/imx8mm-sm2s-u-boot.dtsi | 127 ++ > > arch/arm/dts/imx8mm-sm2s.dts | 16 + > > arch/arm/dts/imx8mm-sm2s.dtsi | 317 +++ > > arch/arm/mach-imx/imx8m/Kconfig | 7 + > > board/avnet/common/Kconfig | 13 + > > board/avnet/common/Makefile | 24 + > > board/avnet/common/boardinfo.c | 200 ++ > > board/avnet/common/boardinfo.h | 105 + > > board/avnet/common/i2c_eeprom.c | 156 ++ > > board/avnet/common/i2c_eeprom.h | 19 + > > board/avnet/common/mmc.c | 49 + > > board/avnet/common/mx8m_common.c | 26 + > > board/avnet/common/mx8m_common.h | 11 + > > board/avnet/imx8mm_sm2s/Kconfig | 12 + > > board/avnet/imx8mm_sm2s/MAINTAINERS | 7 + > > board/avnet/imx8mm_sm2s/Makefile | 12 + > > board/avnet/imx8mm_sm2s/README | 37 + > > board/avnet/imx8mm_sm2s/boardinfo.c | 52 + > > board/avnet/imx8mm_sm2s/ddr_timings.h | 21 + > > board/avnet/imx8mm_sm2s/imx8mm_sm2s.c | 107 + > > No way to split this in a series ? Just to allow us to review it... > > > ...mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c | 1846 +++++++++++++++++ > > > > > board/avnet/imx8mm_sm2s/spl.c | 227 ++ > > configs/imx8mm_sm2s_defconfig | 88 + > > include/configs/imx8mm_sm2s.h | 162 ++ > > 25 files changed, 3642 insertions(+) > > create mode 100644 arch/arm/dts/imx8mm-sm2s-u-boot.dtsi > > create mode 100644 arch/arm/dts/imx8mm-sm2s.dts > > create mode 100644 arch/arm/dts/imx8mm-sm2s.dtsi > > create mode 100644 board/avnet/common/Kconfig > > create mode 100644 board/avnet/common/Makefile > > create mode 100644 board/avnet/common/boardinfo.c > > create mode 100644 board/avnet/common/boardinfo.h > > create mode 100644 board/avnet/common/i2c_eeprom.c > > create mode 100644 board/avnet/common/i2c_eeprom.h > > create mode 100644 board/avnet/common/mmc.c > > create mode 100644 board/avnet/common/mx8m_common.c > > create mode 100644 board/avnet/common/mx8m_common.h > > create mode 100644 board/avnet/imx8mm_sm2s/Kconfig > > create mode 100644 board/avnet/imx8mm_sm2s/MAINTAINERS > > create mode 100644 board/avnet/imx8mm_sm2s/Makefile > > create mode 100644 board/avnet/imx8mm_sm2s/README > > create mode 100644 board/avnet/imx8mm_sm2s/boardinfo.c > > create mode 100644 board/avnet/imx8mm_sm2s/ddr_timings.h > > create mode 100644 board/avnet/imx8mm_sm2s/imx8mm_sm2s.c > > create mode 100644 > board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c > > create mode 100644 board/avnet/imx8mm_sm2s/spl.c > > create mode 100644 configs/imx8mm_sm2s_defconfig > > create mode 100644 include/configs/imx8mm_sm2s.h > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > > index 0127a91a82..dccb58b41a 100644 > > --- a/arch/arm/dts/Makefile > > +++ b/arch/arm/dts/Makefile > > @@ -671,6 +671,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ > > > > dtb-$(CONFIG_ARCH_IMX8M) += \ > > imx8mm-evk.dtb \ > > + imx8mm-sm2s.dtb \ > > imx8mn-ddr4-evk.dtb \ > > imx8mq-evk.dtb > > > > diff --git a/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi > b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi > > new file mode 100644 > > index 0000000000..51d5dc6ea4 > > --- /dev/null > > +++ b/arch/arm/dts/imx8mm-sm2s-u-boot.dtsi > > @@ -0,0 +1,127 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 Amarula Solutions B.V. > > + */ > > + > > +/{ > > + aliases { > > + i2c0 = &i2c1; > > + i2c2 = &i2c3; > > + }; > > +}; > > + > > +&{/soc@0} { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&clk { > > + u-boot,dm-spl; > > + u-boot,dm-pre-reloc; > > + /delete-property/ assigned-clocks; > > + /delete-property/ assigned-clock-parents; > > + /delete-property/ assigned-clock-rates; > > +}; > > + > > +&osc_24m { > > + u-boot,dm-spl; > > + u-boot,dm-pre-reloc; > > +}; > > + > > +&aips1 { > > + u-boot,dm-spl; > > + u-boot,dm-pre-reloc; > > +}; > > + > > +&aips2 { > > + u-boot,dm-spl; > > +}; > > + > > +&aips3 { > > + u-boot,dm-spl; > > + u-boot,dm-pre-reloc; > > +}; > > + > > +&iomuxc { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_usdhc2_gpio { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_usdhc2 { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_usdhc1 { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_usdhc1_reset { > > + u-boot,dm-spl; > > +}; > > + > > +&gpio1 { > > + u-boot,dm-spl; > > +}; > > + > > +&gpio2 { > > + u-boot,dm-spl; > > +}; > > + > > +&gpio3 { > > + u-boot,dm-spl; > > +}; > > + > > +&gpio4 { > > + u-boot,dm-spl; > > +}; > > + > > +&gpio5 { > > + u-boot,dm-spl; > > +}; > > + > > +&uart1 { > > + u-boot,dm-spl; > > +}; > > + > > +&usdhc1 { > > + u-boot,dm-spl; > > +}; > > + > > +&usdhc2 { > > + u-boot,dm-spl; > > +}; > > + > > +&usdhc3 { > > + u-boot,dm-spl; > > +}; > > + > > +&i2c1 { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&i2c3 { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_uart1 { > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_i2c1 { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_i2c3 { > > + u-boot,dm-pre-reloc; > > + u-boot,dm-spl; > > +}; > > + > > +&pinctrl_pmic { > > + u-boot,dm-spl; > > +}; > > diff --git a/arch/arm/dts/imx8mm-sm2s.dts b/arch/arm/dts/imx8mm-sm2s.dts > > new file mode 100644 > > index 0000000000..2e193208f0 > > --- /dev/null > > +++ b/arch/arm/dts/imx8mm-sm2s.dts > > @@ -0,0 +1,16 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 Amarula Solutions B.V. > > + * Copyright 2019 AVNET > > + */ > > + > > +#include "imx8mm-sm2s.dtsi" > > + > > +/ { > > + model = "MSC SM2S-IMX8MM"; > > + compatible = "msc,sm2s-imx8mm", "fsl,imx8mm"; > > + > > + chosen { > > + stdout-path = &uart1; > > + }; > > +}; > > diff --git a/arch/arm/dts/imx8mm-sm2s.dtsi > b/arch/arm/dts/imx8mm-sm2s.dtsi > > new file mode 100644 > > index 0000000000..a6c1f01eea > > --- /dev/null > > +++ b/arch/arm/dts/imx8mm-sm2s.dtsi > > @@ -0,0 +1,317 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 Amarula Solutons B.V. > > + * Copyright 2019 AVNET > > + */ > > + > > +/dts-v1/; > > + > > +#include "imx8mm.dtsi" > > +#include <dt-bindings/usb/pd.h> > > +#include <dt-bindings/net/ti-dp83867.h> > > + > > +/ { > > + extcon_usbotg1: extcon_usbotg1 { > > + compatible = "linux,extcon-usb-gpio"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_extcon_usbotg1>; > > + id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; > > + }; > > + > > + reg_otg1_vbus: otg1_vbus_regulator { > > + compatible = "regulator-fixed"; > > + regulator-name = "OTG1_VBUS"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > +}; > > + > > +&fec1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_fec1>; > > + phy-mode = "rgmii-id"; > > + phy-handle = <ðphy>; > > + fsl,magic-packet; > > + status = "okay"; > > + > > + mdio { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + ethphy: ethernet-phy@1 { > > + reg = <1>; > > + compatible = "ethernet-phy-id2000.a231"; > > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; > > + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; > > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > > + }; > > + }; > > +}; > > + > > +&i2c1 { > > + clock-frequency = <400000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c1>; > > + status = "okay"; > > + > > + rtc: rtc@32 { > > + compatible = "ricoh,r2221tl"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_rtc>; > > + reg = <0x32>; > > + }; > > + > > + tmp103: tmp103@71 { > > + compatible = "ti,tmp103"; > > + reg = <0x71>; > > + }; > > +}; > > + > > +&i2c3 { > > + clock-frequency = <100000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c3>; > > + status = "okay"; > > + > > + eepropm: eeprom@50 { > > + compatible = "atmel,24c64"; > > + reg = <0x50>; > > + }; > > +}; > > + > > +&uart1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart1>; > > + status = "okay"; > > +}; > > + > > +&usdhc1 { > > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > > + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_reset>; > > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_reset>; > > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_reset>; > > + bus-width = <8>; > > + non-removable; > > + status = "okay"; > > +}; > > + > > +&usdhc2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > > + bus-width = <4>; > > + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; > > + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; > > + status = "okay"; > > +}; > > + > > +&usbotg1 { > > + dr_mode = "otg"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbotg1>; > > + usb-role-switch; > > + disable-over-current; > > + hnp-disable; > > + srp-disable; > > + adp-disable; > > + extcon = <0>, <&extcon_usbotg1>; > > + vbus-supply = <®_otg1_vbus>; > > + status = "okay"; > > +}; > > + > > +&usbphynop2 { > > + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > > +}; > > + > > +&usbotg2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usbotg2>; > > + dr_mode = "host"; > > + status = "okay"; > > +}; > > + > > +&wdog1 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_wdog1>; > > + fsl,ext-reset-output; > > + status = "okay"; > > +}; > > + > > +&iomuxc { > > + pinctrl-names = "default"; > > + > > + pinctrl_fec1: fec1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 > > + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 > > + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL > 0x1f > > + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC > 0x1f > > + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 > 0x1f > > + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 > 0x1f > > + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 > 0x1f > > + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 > 0x1f > > + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL > 0x91 > > + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC > 0x91 > > + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 > 0x91 > > + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 > 0x91 > > + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 > 0x91 > > + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 > 0x91 > > + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 > 0x19 > > + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 > 0x40000019 > > + MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN > 0x19 > > + >; > > + }; > > + > > + pinctrl_qspi: qspigrp { > > + fsl,pins = < > > + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK > 0x82 > > + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B > 0x82 > > + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 > 0x82 > > + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 > 0x82 > > + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 > 0x82 > > + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 > 0x82 > > + >; > > + }; > > + > > + pinctrl_i2c1: i2c1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL > 0x400001c3 > > + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA > 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL > 0x400001c3 > > + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA > 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_i2c3: i2c3grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL > 0x400001c3 > > + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA > 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_pmic: pmicirq { > > + fsl,pins = < > > + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 > 0x41 > > + >; > > + }; > > + > > + pinctrl_rtc: rtcgrp { > > + fsl,pins = < > > + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 > 0x40000019 > > + >; > > + }; > > + > > + pinctrl_uart1: uart1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX > 0x49 > > + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX > 0x49 > > + >; > > + }; > > + > > + pinctrl_usdhc1_reset: usdhc1grp-reset { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B > 0x116 > > + >; > > + }; > > + > > + pinctrl_usdhc1: usdhc1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > 0x40000190 > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > 0x1d0 > > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > 0x1d0 > > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > 0x190 > > + >; > > + }; > > + > > + pinctrl_usdhc1_100mhz: usdhc1grp-100mhz { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > 0x40000194 > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > 0x1d4 > > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > 0x1d4 > > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > 0x194 > > + >; > > + }; > > + > > + pinctrl_usdhc1_200mhz: usdhc1grp-200mhz { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK > 0x40000196 > > + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 > 0x1d6 > > + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 > 0x1d6 > > + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE > 0x196 > > + >; > > + }; > > + > > + pinctrl_usdhc2_gpio: usdhc2grp-gpio { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 > 0x41 > > + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 > 0x41 > > + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 > 0x41 > > + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 > 0x41 > > + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT > 0x1d0 > > + >; > > + }; > > + > > + pinctrl_usdhc2: usdhc2grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK > 0x190 > > + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD > 0x1d0 > > + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 > 0x1d0 > > + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 > 0x1d0 > > + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 > 0x1d0 > > + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 > 0x1d0 > > + >; > > + }; > > + > > + pinctrl_wdog1: wdog1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B > 0xc6 > > + >; > > + }; > > + > > + pinctrl_usbotg1: usbotg1grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 > 0x40000019 > > + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC > 0x40000019 > > + >; > > + }; > > + > > + pinctrl_extcon_usbotg1: usbotg1grp-extcon { > > + fsl,pins = < > > + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 > 0x40000019 > > + >; > > + }; > > + > > + pinctrl_usbotg2: usbotg2grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 > 0x40000019 > > + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 > 0x19 > > + >; > > + }; > > +}; > > diff --git a/arch/arm/mach-imx/imx8m/Kconfig > b/arch/arm/mach-imx/imx8m/Kconfig > > index eb4a73b3e2..7a65266fd9 100644 > > --- a/arch/arm/mach-imx/imx8m/Kconfig > > +++ b/arch/arm/mach-imx/imx8m/Kconfig > > @@ -34,6 +34,12 @@ config TARGET_IMX8MM_EVK > > select SUPPORT_SPL > > select IMX8M_LPDDR4 > > > > +config TARGET_IMX8MM_SM2S > > + bool "imx8mm LPDDR4 SM2S board" > > + select IMX8MM > > + select SUPPORT_SPL > > + select IMX8M_LPDDR4 > > + > > config TARGET_IMX8MN_EVK > > bool "imx8mn DDR4 EVK board" > > select IMX8MN > > @@ -45,5 +51,6 @@ endchoice > > source "board/freescale/imx8mq_evk/Kconfig" > > source "board/freescale/imx8mm_evk/Kconfig" > > source "board/freescale/imx8mn_evk/Kconfig" > > +source "board/avnet/imx8mm_sm2s/Kconfig" > > > > endif > > diff --git a/board/avnet/common/Kconfig b/board/avnet/common/Kconfig > > new file mode 100644 > > index 0000000000..6e5d09a504 > > --- /dev/null > > +++ b/board/avnet/common/Kconfig > > @@ -0,0 +1,13 @@ > > +# > > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH > > +# > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > + > > +menu "MSC board/module specific features" > > + > > +config BOARDINFO_EEPROM > > + bool "Board information EEPROM storage" > > + default y > > + help > > + Enable board information storage in EEPROM > > diff --git a/board/avnet/common/Makefile b/board/avnet/common/Makefile > > new file mode 100644 > > index 0000000000..413c95f8d7 > > --- /dev/null > > +++ b/board/avnet/common/Makefile > > @@ -0,0 +1,24 @@ > > +# > > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH > > +# > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > + > > +MINIMAL= > > + > > +ifdef CONFIG_SPL_BUILD > > +ifdef CONFIG_SPL_INIT_MINIMAL > > +MINIMAL=y > > +endif > > +endif > > + > > +ifdef MINIMAL > > +# necessary to create built-in.o > > +obj- := __dummy__.o > > +else > > + > > +obj-y += i2c_eeprom.o > > +obj-y += mmc.o > > +obj-y += boardinfo.o > > +obj-$(CONFIG_IMX8M) += mx8m_common.o > > +endif > > diff --git a/board/avnet/common/boardinfo.c > b/board/avnet/common/boardinfo.c > > new file mode 100644 > > index 0000000000..600054ab01 > > --- /dev/null > > +++ b/board/avnet/common/boardinfo.c > > @@ -0,0 +1,200 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +#include <linux/types.h> > > +#include <linux/errno.h> > > +#include <asm/mach-imx/mxc_i2c.h> > > +#include <i2c.h> > > +#include <command.h> > > +#include <asm/arch/sys_proto.h> > > +#include "string.h" > > +#include "boardinfo.h" > > + > > +static board_info_t board_info; > > + > > +static bool bi_check_magic(const board_info_t *bi) > > +{ > > + if (!bi) > > + goto error; > > + > > + if (bi->head.magic[0] != 'm' || > > + bi->head.magic[1] != 's' || > > + bi->head.magic[2] != 'c' ) > > + goto error; > > + > > + return true; > > + > > +error: > > + BI_DEBUG("Magic check failed. \n"); > > + return false; > > +} > > + > > +static int bi_calc_checksum(const board_info_t *bi, uint16_t *chksum) > > +{ > > + int i; > > + const unsigned char *ptr; > > + > > + if (!bi) > > + return -EINVAL; > > + > > + if (bi->head.version == BI_VER_1_0) { > > + const bi_v1_0_t *body = &BI_GET_BODY(bi, 1, 0); > > + ptr = (const unsigned char*)body; > > + *chksum = 0; > > + for (i = 0; i < sizeof(*body); i++) > > + *chksum += ptr[i]; > > + } else { > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static bool bi_check_checksum(const board_info_t *bi) > > +{ > > + uint16_t chksum; > > + int ret; > > + > > + if (!bi) > > + goto error; > > + > > + ret = bi_calc_checksum(bi, &chksum); > > + if (ret) > > + goto error; > > + > > + if (chksum != bi->head.body_chksum) > > + goto error; > > + > > + return true; > > +error: > > + BI_DEBUG("Magic check failed. \n"); > > + return false; > > +} > > + > > +static bool bi_ckeck(const board_info_t *bi) > > +{ > > + return bi_check_magic(bi) && bi_check_checksum(bi); > > +} > > + > > +void bi_print(const board_info_t *bi) > > +{ > > + if (!bi) > > + return; > > + > > + printf("company .......... %s\n", bi_get_company(bi)); > > + printf("form factor ...... %s\n", bi_get_form_factor(bi)); > > + printf("platform ......... %s\n", bi_get_platform(bi)); > > + printf("processor ........ %s\n", bi_get_processor(bi)); > > + printf("feature .......... %s\n", bi_get_feature(bi)); > > + printf("serial ........... %s\n", bi_get_serial(bi)); > > + printf("revision (MES) ... %s\n", bi_get_revision(bi)); > > + printf("boot count ....... %d\n", bi_get_boot_count(bi)); > > +} > > + > > +__weak int read_boardinfo(board_info_t *bi) > > +{ > > + return -ENODATA; > > +} > > + > > +board_info_t *bi_init(void) > > +{ > > + int ret; > > + > > + memset(&board_info, 0, sizeof(board_info)); > > + > > + ret = read_boardinfo(&board_info); > > + if (ret) > > + goto error; > > + > > + if (!bi_ckeck(&board_info)) { > > + ret = -EINVAL; > > + goto error; > > + } > > + > > + return &board_info; > > + > > +error: > > + memset(&board_info, 0, sizeof(board_info)); > > + return NULL; > > +} > > + > > +__weak int write_boardinfo(board_info_t *bi) > > +{ > > + return -ENODATA; > > +} > > + > > +int bi_save(board_info_t *bi) > > +{ > > + bi_head_t *head; > > + uint16_t chksum = 0; > > + > > + if (bi == NULL) return -ENODATA; > > + > > + head = &bi->head; > > + head->magic[0] = 'm'; > > + head->magic[1] = 's'; > > + head->magic[2] = 'c'; > > + head->version = BI_CALC_VER(1, 0); > > + bi_calc_checksum(bi, &chksum); > > + head->body_chksum = chksum; > > + head->body_off = sizeof(bi_head_t); > > + head->body_len = sizeof(bi_v1_0_t); > > + > > + return write_boardinfo(bi); > > +} > > + > > +const char* bi_get_company(const board_info_t *bi) > > +{ > > + if (BI_HAS_FEATURE(bi, COMPANY)) > > + return BI_GET_BODY(bi, 1, 0).company; > > + return "N/A"; > > +} > > + > > +__weak const char* bi_get_form_factor(const board_info_t *bi) > > +{ > > + return "N/A"; > > +} > > + > > +__weak const char* bi_get_platform(const board_info_t *bi) > > +{ > > + return "N/A"; > > +} > > + > > +__weak const char* bi_get_processor(const board_info_t *bi) > > +{ > > + return "N/A"; > > +} > > + > > +const char* bi_get_feature(const board_info_t *bi) > > +{ > > + if (BI_HAS_FEATURE(bi, FEATURE)) > > + return BI_GET_BODY(bi, 1, 0).feature; > > + return "N/A"; > > +} > > + > > +const char* bi_get_serial(const board_info_t *bi) > > +{ > > + if (BI_HAS_FEATURE(bi, SERIAL)) > > + return BI_GET_BODY(bi, 1, 0).serial_number; > > + return "N/A"; > > +} > > + > > +const char* bi_get_revision(const board_info_t *bi) > > +{ > > + if (BI_HAS_FEATURE(bi, REVISION)) > > + return BI_GET_BODY(bi, 1, 0).revision; > > + return "N/A"; > > +} > > + > > +int bi_inc_boot_count(board_info_t *bi) > > +{ > > + BI_GET_BODY(bi, 1 , 0).boot_count += 1; > > + return bi_save(bi); > > +} > > + > > +uint32_t bi_get_boot_count(const board_info_t *bi) > > +{ > > + return BI_GET_BODY(bi, 1, 0).boot_count; > > +} > > diff --git a/board/avnet/common/boardinfo.h > b/board/avnet/common/boardinfo.h > > new file mode 100644 > > index 0000000000..131592dbcd > > --- /dev/null > > +++ b/board/avnet/common/boardinfo.h > > @@ -0,0 +1,105 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +#ifndef __MSC_BOARDINFO_H__ > > +#define __MSC_BOARDINFO_H__ > > + > > +#define BI_VER_MAJ 1 > > +#define BI_VER_MIN 0 > > + > > +#define BI_COMPANY_LEN 3 > > +#define BI_FEATURE_LEN 8 > > +#define BI_SERIAL_LEN 11 > > +#define BI_REVISION_LEN 2 > > + > > +#define BI_COMPANY_BIT (1<<0) > > +#define BI_FEATURE_BIT (1<<1) > > +#define BI_SERIAL_BIT (1<<2) > > +#define BI_REVISION_BIT (1<<3) > > + > > +typedef struct bi_head { > > + uint8_t magic[4]; > > + uint8_t version; > > + uint8_t v_min; > > + uint16_t body_len; > > + uint16_t body_off; > > + uint16_t body_chksum; > > + uint32_t reserved[2]; > > +} bi_head_t; > > + > > +typedef struct bi_v1_0 { > > + uint32_t __feature_bits; > > + char company [BI_COMPANY_LEN + 1]; > > + char feature[BI_FEATURE_LEN + 1]; > > + char serial_number[BI_SERIAL_LEN + 1]; > > + char revision[BI_REVISION_LEN + 1]; > > + uint32_t boot_count; > > + uint16_t reserved; > > +} bi_v1_0_t; > > + > > +typedef struct board_info { > > + bi_head_t head; > > + union { > > + bi_v1_0_t v1_0; > > + } body; > > +} board_info_t; > > + > > +#define BI_STR "Boardinfo" > > + > > +#define BI_CALC_VER(MAJ, MIN) \ > > + ((MAJ)<<4 | (MIN)) > > + > > +#define BI_VER_1_0 BI_CALC_VER (1, 0) > > + > > +#define BI_HAS_FEATURE(BI, F) \ > > + ((BI)->body.v1_0.__feature_bits & BI_##F##_BIT) > > + > > +#define BI_ENABLE_FEATURE(BI, F) \ > > + do { \ > > + (BI)->body.v1_0.__feature_bits |= BI_##F##_BIT; \ > > + } \ > > + while(0); > > + > > +#define BI_GET_BODY(BI, MAJ, MIN) \ > > + ((BI)->body.v##MAJ##_##MIN) > > + > > +#define BI_PRINT(format, ...) \ > > + do { \ > > + printf("%s: ", BI_STR); \ > > + printf(format, ## __VA_ARGS__); \ > > + } \ > > + while(0); > > + > > +#if defined(DEBUG) > > + #define BI_DEBUG(format, ...) \ > > + do { \ > > + printf("%s: ", BI_STR); \ > > + printf(format, ## __VA_ARGS__); \ > > + } \ > > + while(0); > > +#else /* defined(DEBUG) */ > > + #define BI_DEBUG(format, ...) > > +#endif /* defined(DEBUG) */ > > + > > +board_info_t *bi_init(void); > > + > > +const char* bi_get_company(const board_info_t *bi); > > +const char* bi_get_form_factor(const board_info_t *bi); > > +const char* bi_get_platform(const board_info_t *bi); > > +const char* bi_get_processor(const board_info_t *bi); > > +const char* bi_get_feature(const board_info_t *bi); > > +const char* bi_get_serial(const board_info_t *bi); > > +const char* bi_get_revision(const board_info_t *bi); > > +uint32_t bi_get_boot_count(const board_info_t *bi); > > + > > +int bi_inc_boot_count(board_info_t *bi); > > + > > +void bi_print(const board_info_t *bi); > > + > > +#if !defined(CONFIG_SPL_BUILD) > > + int bi_save(board_info_t *bi); > > +#endif /* !defined(CONFIG_SPL_BUILD) */ > > + > > +#endif /* __MSC_BOARDINFO_H__ */ > > diff --git a/board/avnet/common/i2c_eeprom.c > b/board/avnet/common/i2c_eeprom.c > > new file mode 100644 > > index 0000000000..98e870fd6c > > --- /dev/null > > +++ b/board/avnet/common/i2c_eeprom.c > > @@ -0,0 +1,156 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +#include <common.h> > > +#include <config.h> > > +#include <linux/types.h> > > +#include <linux/errno.h> > > +#include <i2c.h> > > +#include <command.h> > > +#include "i2c_eeprom.h" > > + > > +// #define __DEBUG__ > > + > > +#ifndef CONFIG_SYS_EEPROM_PAGE_WRITE_BITS > > + #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 8 > > +#endif > > +#define EEPROM_PAGE_SIZE (1 << > CONFIG_SYS_EEPROM_PAGE_WRITE_BITS) > > +#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1)) > > + > > +__weak int i2c_eeprom_write_enable(const i2c_eeprom_t *eeprom, int > state) > > +{ > > + return 0; > > +} > > + > > +static int i2c_eeprom_addr(const i2c_eeprom_t *eeprom, unsigned offset, > uchar *addr) > > +{ > > + unsigned blk_off; > > + > > + blk_off = offset & 0xff; /* block offset */ > > + > > + if (eeprom->alen == 1) { > > + addr[0] = offset >> 8; /* block number */ > > + addr[1] = blk_off; /* block offset */ > > + } else { > > + addr[0] = offset >> 16; /* block number */ > > + addr[1] = offset >> 8; /* upper address octet */ > > + addr[2] = blk_off; /* lower address octet */ > > + } > > + > > + addr[0] |= eeprom->dev_addr; /* insert device address */ > > + > > + return 0; > > +} > > + > > +static int i2c_eeprom_len(const i2c_eeprom_t *eeprom, unsigned offset, > unsigned end) > > +{ > > + unsigned len = end - offset; > > + unsigned blk_off = offset & 0xff; > > + unsigned maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off); > > + > > + if (maxlen > eeprom->rw_blk_size) > > + maxlen = eeprom->rw_blk_size; > > + > > + if (len > maxlen) > > + len = maxlen; > > + > > + return len; > > +} > > + > > +static int i2c_eeprom_rw_block(const i2c_eeprom_t *eeprom, unsigned > offset, uchar *addr, > > + uchar *buffer, unsigned len, bool read) > > +{ > > + int ret = 0; > > + > > +#if defined(CONFIG_DM_I2C) > > + struct udevice *dev; > > + > > + ret = i2c_get_chip_for_busnum(eeprom->bus_id, addr[0], > eeprom->alen, &dev); > > + if (ret) { > > + printf("Cannot find udev for bus %d\n", eeprom->bus_id); > > + return -ENODEV; > > + } > > + > > + if (read) > > + ret = dm_i2c_read(dev, offset, buffer, len); > > + else > > + ret = dm_i2c_write(dev, offset, buffer, len); > > + > > +#else > > + > > + if (read) > > + ret = i2c_read(addr[0], offset, eeprom->alen, buffer, len); > > + else > > + ret = i2c_write(addr[0], offset, eeprom->alen, buffer, > len); > > +#endif > > + > > + if (ret) > > + ret = 1; > > + > > + return ret; > > +} > > + > > +static int i2c_eeprom_rw(const i2c_eeprom_t *eeprom, unsigned offset, > uchar *buffer, > > + unsigned cnt, bool read) > > +{ > > + unsigned end = offset + cnt; > > + unsigned len; > > + int rcode = 0; > > + uchar addr[3]; > > + > > + while (offset < end) { > > + i2c_eeprom_addr(eeprom, offset, addr); > > + len = i2c_eeprom_len(eeprom, offset, end); > > + > > + rcode = i2c_eeprom_rw_block(eeprom, offset, addr, buffer, > len, read); > > + > > + buffer += len; > > + offset += len; > > + > > + if (!read) > > + mdelay(eeprom->write_delay_ms); > > + } > > + > > + return rcode; > > +} > > + > > +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar > *buffer, unsigned cnt) > > +{ > > +#if defined(CONFIG_SYS_I2C) > > + if (eeprom->bus_id >= 0) > > + i2c_set_bus_num(eeprom->bus_id); > > +#endif > > + > > + /* > > + * Read data until done or would cross a page boundary. > > + * We must write the address again when changing pages > > + * because the next page may be in a different device. > > + */ > > + return i2c_eeprom_rw(eeprom, offset, buffer, cnt, 1); > > +} > > + > > +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar > *buffer, unsigned cnt) > > +{ > > + int ret; > > + > > + > > +#if defined(CONFIG_SYS_I2C) > > + if (eeprom->bus_id >= 0) > > + i2c_set_bus_num(eeprom->bus_id); > > +#endif > > + > > + i2c_eeprom_write_enable(eeprom, 1); > > + > > + /* > > + * Write data until done or would cross a write page boundary. > > + * We must write the address again when changing pages > > + * because the address counter only increments within a page. > > + */ > > + ret = i2c_eeprom_rw(eeprom, offset, buffer, cnt, 0); > > + > > + i2c_eeprom_write_enable(eeprom, 0); > > + > > + return ret; > > +} > > diff --git a/board/avnet/common/i2c_eeprom.h > b/board/avnet/common/i2c_eeprom.h > > new file mode 100644 > > index 0000000000..4dc4657f11 > > --- /dev/null > > +++ b/board/avnet/common/i2c_eeprom.h > > @@ -0,0 +1,19 @@ > > +#ifndef __MSC_I2C_EEPROM_H__ > > +#define __MSC_I2C_EEPROM_H__ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +typedef struct i2c_eeprom { > > + unsigned bus_id; > > + unsigned dev_addr; > > + unsigned alen; > > + unsigned rw_blk_size; > > + unsigned write_delay_ms; > > +} i2c_eeprom_t; > > + > > +int i2c_eeprom_read(const i2c_eeprom_t *eeprom, unsigned offset, uchar > *buffer, unsigned cnt); > > +int i2c_eeprom_write(const i2c_eeprom_t *eeprom, unsigned offset, uchar > *buffer, unsigned cnt); > > + > > +#endif /* __MSC_I2C_EEPROM_H__ */ > > diff --git a/board/avnet/common/mmc.c b/board/avnet/common/mmc.c > > new file mode 100644 > > index 0000000000..380a2df35f > > --- /dev/null > > +++ b/board/avnet/common/mmc.c > > @@ -0,0 +1,49 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +#include <common.h> > > +#include <asm/arch/sys_proto.h> > > +#include <linux/errno.h> > > +#include <asm/io.h> > > +#include <stdbool.h> > > +#include <mmc.h> > > + > > +static int check_mmc_autodetect(void) > > +{ > > + char *autodetect_str = env_get("mmcautodetect"); > > + > > + if ((autodetect_str != NULL) && > > + (strcmp(autodetect_str, "yes") == 0)) { > > + return 1; > > + } > > + > > + return 0; > > +} > > + > > +/* This should be defined for each board */ > > +__weak int mmc_map_to_kernel_blk(int dev_no) > > +{ > > + return dev_no; > > +} > > + > > +void board_late_mmc_env_init(void) > > +{ > > + char cmd[32]; > > + char mmcblk[32]; > > + u32 dev_no = mmc_get_env_dev(); > > + > > + if (!check_mmc_autodetect()) > > + return; > > + > > + env_set_ulong("mmcdev", dev_no); > > + > > + /* Set mmcblk env */ > > + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", > > + mmc_map_to_kernel_blk(dev_no)); > > + env_set("mmcroot", mmcblk); > > + > > + sprintf(cmd, "mmc dev %d", dev_no); > > + run_command(cmd, 0); > > +} > > diff --git a/board/avnet/common/mx8m_common.c > b/board/avnet/common/mx8m_common.c > > new file mode 100644 > > index 0000000000..42dddf6ae9 > > --- /dev/null > > +++ b/board/avnet/common/mx8m_common.c > > @@ -0,0 +1,26 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +#include <asm/arch/sys_proto.h> > > +#include "mx8m_common.h" > > + > > +const char* mx8m_get_plat_str(void) > > +{ > > + switch (get_cpu_type()) { > > + case MXC_CPU_IMX8MM: > > + return "imx8mm"; > > + } > > + > > + return "N/A"; > > +} > > + > > +const char* mx8m_get_proc_str(void) > > +{ > > + switch (get_cpu_type()) { > > + case MXC_CPU_IMX8MM: > > + return "qc"; > > + } > > + return "N/A"; > > +} > > diff --git a/board/avnet/common/mx8m_common.h > b/board/avnet/common/mx8m_common.h > > new file mode 100644 > > index 0000000000..bf6e25cbc8 > > --- /dev/null > > +++ b/board/avnet/common/mx8m_common.h > > @@ -0,0 +1,11 @@ > > +#ifndef __MSC_MX8M_COMMON_H__ > > +#define __MSC_MX8M_COMMON_H__ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019 AVNET > > + */ > > + > > +const char* mx8m_get_plat_str(void); > > +const char* mx8m_get_proc_str(void); > > + > > +#endif /* __MSC_MX8M_COMMON_H__ */ > > diff --git a/board/avnet/imx8mm_sm2s/Kconfig > b/board/avnet/imx8mm_sm2s/Kconfig > > new file mode 100644 > > index 0000000000..535adb351a > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/Kconfig > > @@ -0,0 +1,12 @@ > > +if TARGET_IMX8MM_SM2S > > + > > +config SYS_BOARD > > + default "imx8mm_sm2s" > > + > > +config SYS_VENDOR > > + default "avnet" > > + > > +config SYS_CONFIG_NAME > > + default "imx8mm_sm2s" > > + > > +endif > > diff --git a/board/avnet/imx8mm_sm2s/MAINTAINERS > b/board/avnet/imx8mm_sm2s/MAINTAINERS > > new file mode 100644 > > index 0000000000..2dc63ae26d > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/MAINTAINERS > > @@ -0,0 +1,7 @@ > > +i.MX8MM SM2S BOARD > > +M: Michael Trimarchi <[email protected]> > > +M: Waldemar Glensk <[email protected]> > > +S: Maintained > > +F: board/avnet/imx8mm_sm2s/ > > +F: include/configs/imx8mm_sm2s.h > > +F: configs/imx8mm_sm2s_defconfig > > diff --git a/board/avnet/imx8mm_sm2s/Makefile > b/board/avnet/imx8mm_sm2s/Makefile > > new file mode 100644 > > index 0000000000..56df9d79b4 > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/Makefile > > @@ -0,0 +1,12 @@ > > +# > > +# Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH > > +# > > +# SPDX-License-Identifier: GPL-2.0+ > > +# > > + > > +obj-y += imx8mm_sm2s.o boardinfo.o > > + > > +ifdef CONFIG_SPL_BUILD > > +obj-y += spl.o > > +obj-$(CONFIG_IMX8M_LPDDR4) += > lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.o > > +endif > > diff --git a/board/avnet/imx8mm_sm2s/README > b/board/avnet/imx8mm_sm2s/README > > new file mode 100644 > > index 0000000000..4b628b64a0 > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/README > > @@ -0,0 +1,37 @@ > > +U-Boot for the AVNET i.MX8MM SM2S board > > + > > +Quick Start > > +=========== > > +- Build the ARM Trusted firmware binary > > +- Get ddr fimware > > +- Build U-Boot > > +- Boot > > + > > +Get and Build the ARM Trusted firmware > > +====================================== > > +Note: srctree is U-Boot source directory > > +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf > > +branch: imx_4.19.35_1.1.0 > > +$ make PLAT=imx8mm bl31 > > +$ cp build/imx8mm/release/bl31.bin $(srctree) > > + > > +Get the ddr and hdmi firmware > > +============================= > > +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin > > +$ chmod +x firmware-imx-7.9.bin > > +$ ./firmware-imx-7.9 > > +$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctree) > > + > > +Build U-Boot > > +============ > > +$ export CROSS_COMPILE=aarch64-poky-linux- > > +$ make imx8mm_sm2s_defconfig > > +$ export ATF_LOAD_ADDR=0x920000 > > +$ make flash.bin > > + > > +Burn the flash.bin to MicroSD card offset 33KB > > +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 > > + > > +Boot > > +==== > > +Set Boot switch to SD boot > > diff --git a/board/avnet/imx8mm_sm2s/boardinfo.c > b/board/avnet/imx8mm_sm2s/boardinfo.c > > new file mode 100644 > > index 0000000000..c3c705a559 > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/boardinfo.c > > @@ -0,0 +1,52 @@ > > +/* > > + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > > + * kind, whether express or implied; without even the implied warranty > > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include <common.h> > > +#include <malloc.h> > > +#include <errno.h> > > +#include "../common/i2c_eeprom.h" > > +#include "../common/boardinfo.h" > > +#include "../common/mx8m_common.h" > > + > > +i2c_eeprom_t boardinfo_eeprom = { > > + .bus_id = BI_EEPROM_I2C_BUS_ID, > > + .dev_addr = BI_EEPROM_I2C_ADDR, > > + .alen = 2, > > + .rw_blk_size = 16, > > + .write_delay_ms = 5, > > +}; > > + > > +int read_boardinfo(board_info_t *bi) > > +{ > > + return i2c_eeprom_read(&boardinfo_eeprom, 0, (uint8_t*)bi, > sizeof(*bi)); > > +} > > + > > +int write_boardinfo(board_info_t *bi) > > +{ > > + return i2c_eeprom_write(&boardinfo_eeprom, 0, (uint8_t*)bi, > sizeof(*bi)); > > +} > > + > > +const char* bi_get_form_factor(const board_info_t *bi) > > +{ > > + return "sm2s"; > > +} > > + > > +const char* bi_get_platform(const board_info_t *bi) > > +{ > > + return mx8m_get_plat_str(); > > +} > > + > > +const char* bi_get_processor(const board_info_t *bi) > > +{ > > + return mx8m_get_proc_str(); > > +} > > diff --git a/board/avnet/imx8mm_sm2s/ddr_timings.h > b/board/avnet/imx8mm_sm2s/ddr_timings.h > > new file mode 100644 > > index 0000000000..d4b39cdb27 > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/ddr_timings.h > > @@ -0,0 +1,21 @@ > > +#ifndef SM2S_IMX8MM_DDR_TIMINGS_H > > +#define SM2S_IMX8MM_DDR_TIMINGS_H > > + > > +/* > > + * Copyright (C) 2019 AVNET Integrated, MSC Technologies GmbH > > + * > > + * This program is free software; you can redistribute it and/or > > + * modify it under the terms of the GNU General Public License as > > + * published by the Free Software Foundation version 2. > > + * > > + * This program is distributed "as is" WITHOUT ANY WARRANTY of any > > + * kind, whether express or implied; without even the implied warranty > > + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +extern struct dram_timing_info > lpddr4_mt53d512m32d2ds_1gib_2chn_1cs_dv1_timing; > > +extern struct dram_timing_info > lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing; > > +extern struct dram_timing_info > lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv2_timing; > > + > > +#endif /* SM2S_IMX8MM_DDR_TIMINGS_H */ > > diff --git a/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c > b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c > > new file mode 100644 > > index 0000000000..71c12feac9 > > --- /dev/null > > +++ b/board/avnet/imx8mm_sm2s/imx8mm_sm2s.c > > @@ -0,0 +1,107 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 Amarula Solutions B.V. > > + * Copyright 2019 AVNET > > + */ > > + > > +#include <common.h> > > +#include <spl.h> > > +#include <malloc.h> > > +#include <errno.h> > > +#include <asm/io.h> > > +#include <miiphy.h> > > +#include <netdev.h> > > +#include <asm/mach-imx/iomux-v3.h> > > +#include <asm-generic/gpio.h> > > +#include <fsl_esdhc.h> > > +#include <mmc.h> > > +#include <asm/arch/imx8mm_pins.h> > > +#include <asm/arch/sys_proto.h> > > +#include <asm/mach-imx/gpio.h> > > +#include <asm/mach-imx/mxc_i2c.h> > > +#include <asm/mach-imx/dma.h> > > +#include <asm/arch/clock.h> > > +#include <handoff.h> > > +#include <bloblist.h> > > +#include <dt-bindings/net/ti-dp83867.h> > > +#include "../common/i2c_eeprom.h" > > +#include "../common/boardinfo.h" > > +#include "../common/mx8m_common.h" > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +const board_info_t *binfo = NULL; > > + > > +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) > > + > > +#ifdef CONFIG_BOARD_POSTCLK_INIT > > +int board_postclk_init(void) > > +{ > > + return 0; > > +} > > +#endif > > + > > +int dram_init(void) > > +{ > > + struct spl_handoff *ho; > > + > > + ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho)); > > + if (!ho) > > + return log_msg_ret("Missing SPL hand-off info", -ENOENT); > > + handoff_load_dram_size(ho); > > + > > + /* rom_pointer[1] contains the size of TEE occupies */ > > + if (rom_pointer[1]) > > + gd->ram_size -= rom_pointer[1]; > > + > > + return 0; > > +} > > + > > +#ifdef CONFIG_OF_BOARD_SETUP > > +int ft_board_setup(void *blob, bd_t *bd) > > +{ > > + return 0; > > +} > > +#endif > > + > > +int board_init(void) > > +{ > > +#if !defined(CONFIG_SPL_BUILD) > > + binfo = bi_init(); > > + if (binfo == NULL) { > > + printf("Warning: failed to initialize boardinfo!\n"); > > + } > > +#endif /* !defined(CONFIG_SPL_BUILD) */ > > + > > + return 0; > > +} > > + > > +int board_mmc_get_env_dev(int devno) > > +{ > > + return devno; > > +} > > + > > +#define ENV_FDTFILE_MAX_SIZE 64 > > + > > +#if !defined(CONFIG_SPL_BUILD) > > +int board_late_init(void) > > +{ > > + char buff[ENV_FDTFILE_MAX_SIZE]; > > + char *fdtfile; > > + > > + if (!binfo) > > + return 0; > > + > > + fdtfile = env_get("fdt_file"); > > + if (fdtfile) > > + return 0; > > + > > + snprintf(buff, ENV_FDTFILE_MAX_SIZE, "%s-%s-%s-%s-%s.dtb", > > + bi_get_company(binfo), bi_get_form_factor(binfo), > > + bi_get_platform(binfo), bi_get_processor(binfo), > > + bi_get_feature(binfo)); > > + env_set("fdt_file", buff); > > + > > + return 0; > > +} > > +#endif /* !defined(CONFIG_SPL_BUILD) */ > > diff --git > a/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c > b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c > > new file mode 100644 > > index 0000000000..9c37afeb11 > > --- /dev/null > > +++ > b/board/avnet/imx8mm_sm2s/lpddr4_mt53d512m32d2ds_2gib_2chn_2cs_dv1_timing.c > > @@ -0,0 +1,1846 @@ > > +/* > > + * Copyright 2018 NXP > > + * > > + * SPDX-License-Identifier: GPL-2.0+ > > + * > > + * Generated code from MX8M_DDR_tool > > + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga > > + */ > > + > > +#include <linux/kernel.h> > > +#include <asm/arch/ddr.h> > > + > > +static struct dram_cfg_param ddr_ddrc_cfg[] = { > > + /** Initialize DDRC registers **/ > > + {0x3d400304, 0x1}, > > + {0x3d400030, 0x1}, > > + {0x3d400000, 0xa3080020}, > > + {0x3d400020, 0x223}, > > + {0x3d400024, 0x3a980}, > > + {0x3d400064, 0x5b0087}, > > + {0x3d4000d0, 0xc00305ba}, > > + {0x3d4000d4, 0x940000}, > > + {0x3d4000dc, 0xd4002d}, > > + {0x3d4000e0, 0x310000}, > > + {0x3d4000e8, 0x66004d}, > > + {0x3d4000ec, 0x16004d}, > > + {0x3d400100, 0x191e1920}, > > + {0x3d400104, 0x60630}, > > + {0x3d40010c, 0xb0b000}, > > + {0x3d400110, 0xe04080e}, > > + {0x3d400114, 0x2040c0c}, > > + {0x3d400118, 0x1010007}, > > + {0x3d40011c, 0x401}, > > + {0x3d400130, 0x20600}, > > + {0x3d400134, 0xc100002}, > > + {0x3d400138, 0x8d}, > > + {0x3d400144, 0x96004b}, > > + {0x3d400180, 0x2ee0017}, > > + {0x3d400184, 0x2605b8e}, > > + {0x3d400188, 0x0}, > > + {0x3d400190, 0x497820a}, > > + {0x3d400194, 0x80303}, > > + {0x3d4001b4, 0x170a}, > > + {0x3d4001a0, 0xe0400018}, > > + {0x3d4001a4, 0xdf00e4}, > > + {0x3d4001a8, 0x80000000}, > > + {0x3d4001b0, 0x11}, > > + {0x3d4001c0, 0x1}, > > + {0x3d4001c4, 0x0}, > > + {0x3d4000f4, 0xc99}, > > + {0x3d400108, 0x70e1617}, > > + {0x3d400200, 0x16}, > > + {0x3d40020c, 0x0}, > > + {0x3d400210, 0x1f1f}, > > + {0x3d400204, 0x80808}, > > + {0x3d400214, 0x7070707}, > > + {0x3d400218, 0xf070707}, > > + {0x3d400250, 0x29001701}, > > + {0x3d400254, 0x2c}, > > + {0x3d40025c, 0x4000030}, > > + {0x3d400264, 0x900093e7}, > > + {0x3d40026c, 0x2005574}, > > + {0x3d400400, 0x111}, > > + {0x3d400408, 0x72ff}, > > + {0x3d400494, 0x2100e07}, > > + {0x3d400498, 0x620096}, > > + {0x3d40049c, 0x1100e07}, > > + {0x3d4004a0, 0xc8012c}, > > + {0x3d402020, 0x21}, > > + {0x3d402024, 0x7d00}, > > + {0x3d402050, 0x20d040}, > > + {0x3d402064, 0xc0012}, > > + {0x3d4020dc, 0x840000}, > > + {0x3d4020e0, 0x310000}, > > + {0x3d4020e8, 0x66004d}, > > + {0x3d4020ec, 0x16004d}, > > + {0x3d402100, 0xa040305}, > > + {0x3d402104, 0x30407}, > > + {0x3d402108, 0x203060b}, > > + {0x3d40210c, 0x505000}, > > + {0x3d402110, 0x2040202}, > > + {0x3d402114, 0x2030202}, > > + {0x3d402118, 0x1010004}, > > + {0x3d40211c, 0x301}, > > + {0x3d402130, 0x20300}, > > + {0x3d402134, 0xa100002}, > > + {0x3d402138, 0x13}, > > + {0x3d402144, 0x14000a}, > > + {0x3d402180, 0x640004}, > > + {0x3d402190, 0x3818200}, > > + {0x3d402194, 0x80303}, > > + {0x3d4021b4, 0x100}, > > + {0x3d403020, 0x21}, > > + {0x3d403024, 0x1f40}, > > + {0x3d403050, 0x20d040}, > > + {0x3d403064, 0x30005}, > > + {0x3d4030dc, 0x840000}, > > + {0x3d4030e0, 0x310000}, > > + {0x3d4030e8, 0x66004d}, > > + {0x3d4030ec, 0x16004d}, > > + {0x3d403100, 0xa010102}, > > + {0x3d403104, 0x30404}, > > + {0x3d403108, 0x203060b}, > > + {0x3d40310c, 0x505000}, > > + {0x3d403110, 0x2040202}, > > + {0x3d403114, 0x2030202}, > > + {0x3d403118, 0x1010004}, > > + {0x3d40311c, 0x301}, > > + {0x3d403130, 0x20300}, > > + {0x3d403134, 0xa100002}, > > + {0x3d403138, 0x5}, > > + {0x3d403144, 0x50003}, > > + {0x3d403180, 0x190004}, > > + {0x3d403190, 0x3818200}, > > + {0x3d403194, 0x80303}, > > + {0x3d4031b4, 0x100}, > > + {0x3d400028, 0x0}, > > +}; > > + > > +/* PHY Initialize Configuration */ > > +static struct dram_cfg_param ddr_ddrphy_cfg[] = { > > + {0x100a0, 0x0}, > > + {0x100a1, 0x1}, > > + {0x100a2, 0x2}, > > + {0x100a3, 0x3}, > > + {0x100a4, 0x4}, > > + {0x100a5, 0x5}, > > + {0x100a6, 0x6}, > > + {0x100a7, 0x7}, > > + {0x110a0, 0x0}, > > + {0x110a1, 0x1}, > > + {0x110a2, 0x3}, > > + {0x110a3, 0x4}, > > + {0x110a4, 0x5}, > > + {0x110a5, 0x2}, > > + {0x110a6, 0x7}, > > + {0x110a7, 0x6}, > > + {0x120a0, 0x0}, > > + {0x120a1, 0x1}, > > + {0x120a2, 0x3}, > > + {0x120a3, 0x2}, > > + {0x120a4, 0x5}, > > + {0x120a5, 0x4}, > > + {0x120a6, 0x7}, > > + {0x120a7, 0x6}, > > + {0x130a0, 0x0}, > > + {0x130a1, 0x1}, > > + {0x130a2, 0x2}, > > + {0x130a3, 0x3}, > > + {0x130a4, 0x4}, > > + {0x130a5, 0x5}, > > + {0x130a6, 0x6}, > > + {0x130a7, 0x7}, > > + {0x1005f, 0x1ff}, > > + {0x1015f, 0x1ff}, > > + {0x1105f, 0x1ff}, > > + {0x1115f, 0x1ff}, > > + {0x1205f, 0x1ff}, > > + {0x1215f, 0x1ff}, > > + {0x1305f, 0x1ff}, > > + {0x1315f, 0x1ff}, > > + {0x11005f, 0x1ff}, > > + {0x11015f, 0x1ff}, > > + {0x11105f, 0x1ff}, > > + {0x11115f, 0x1ff}, > > + {0x11205f, 0x1ff}, > > + {0x11215f, 0x1ff}, > > + {0x11305f, 0x1ff}, > > + {0x11315f, 0x1ff}, > > + {0x21005f, 0x1ff}, > > + {0x21015f, 0x1ff}, > > + {0x21105f, 0x1ff}, > > + {0x21115f, 0x1ff}, > > + {0x21205f, 0x1ff}, > > + {0x21215f, 0x1ff}, > > + {0x21305f, 0x1ff}, > > + {0x21315f, 0x1ff}, > > + {0x55, 0x1ff}, > > + {0x1055, 0x1ff}, > > + {0x2055, 0x1ff}, > > + {0x3055, 0x1ff}, > > + {0x4055, 0x1ff}, > > + {0x5055, 0x1ff}, > > + {0x6055, 0x1ff}, > > + {0x7055, 0x1ff}, > > + {0x8055, 0x1ff}, > > + {0x9055, 0x1ff}, > > + {0x200c5, 0x19}, > > + {0x1200c5, 0x7}, > > + {0x2200c5, 0x7}, > > + {0x2002e, 0x2}, > > + {0x12002e, 0x2}, > > + {0x22002e, 0x2}, > > + {0x90204, 0x0}, > > + {0x190204, 0x0}, > > + {0x290204, 0x0}, > > + {0x20024, 0x1ab}, > > + {0x2003a, 0x0}, > > + {0x120024, 0x1ab}, > > + {0x2003a, 0x0}, > > + {0x220024, 0x1ab}, > > + {0x2003a, 0x0}, > > + {0x20056, 0x3}, > > + {0x120056, 0xa}, > > + {0x220056, 0xa}, > > + {0x1004d, 0xe00}, > > + {0x1014d, 0xe00}, > > + {0x1104d, 0xe00}, > > + {0x1114d, 0xe00}, > > + {0x1204d, 0xe00}, > > + {0x1214d, 0xe00}, > > + {0x1304d, 0xe00}, > > + {0x1314d, 0xe00}, > > + {0x11004d, 0xe00}, > > + {0x11014d, 0xe00}, > > + {0x11104d, 0xe00}, > > + {0x11114d, 0xe00}, > > + {0x11204d, 0xe00}, > > + {0x11214d, 0xe00}, > > + {0x11304d, 0xe00}, > > + {0x11314d, 0xe00}, > > + {0x21004d, 0xe00}, > > + {0x21014d, 0xe00}, > > + {0x21104d, 0xe00}, > > + {0x21114d, 0xe00}, > > + {0x21204d, 0xe00}, > > + {0x21214d, 0xe00}, > > + {0x21304d, 0xe00}, > > + {0x21314d, 0xe00}, > > + {0x10049, 0xeba}, > > + {0x10149, 0xeba}, > > + {0x11049, 0xeba}, > > + {0x11149, 0xeba}, > > + {0x12049, 0xeba}, > > + {0x12149, 0xeba}, > > + {0x13049, 0xeba}, > > + {0x13149, 0xeba}, > > + {0x110049, 0xeba}, > > + {0x110149, 0xeba}, > > + {0x111049, 0xeba}, > > + {0x111149, 0xeba}, > > + {0x112049, 0xeba}, > > + {0x112149, 0xeba}, > > + {0x113049, 0xeba}, > > + {0x113149, 0xeba}, > > + {0x210049, 0xeba}, > > + {0x210149, 0xeba}, > > + {0x211049, 0xeba}, > > + {0x211149, 0xeba}, > > + {0x212049, 0xeba}, > > + {0x212149, 0xeba}, > > + {0x213049, 0xeba}, > > + {0x213149, 0xeba}, > > + {0x43, 0x63}, > > + {0x1043, 0x63}, > > + {0x2043, 0x63}, > > + {0x3043, 0x63}, > > + {0x4043, 0x63}, > > + {0x5043, 0x63}, > > + {0x6043, 0x63}, > > + {0x7043, 0x63}, > > + {0x8043, 0x63}, > > + {0x9043, 0x63}, > > + {0x20018, 0x3}, > > + {0x20075, 0x4}, > > + {0x20050, 0x0}, > > + {0x20008, 0x2ee}, > > + {0x120008, 0x64}, > > + {0x220008, 0x19}, > > + {0x20088, 0x9}, > > + {0x200b2, 0xdc}, > > + {0x10043, 0x5a1}, > > + {0x10143, 0x5a1}, > > + {0x11043, 0x5a1}, > > + {0x11143, 0x5a1}, > > + {0x12043, 0x5a1}, > > + {0x12143, 0x5a1}, > > + {0x13043, 0x5a1}, > > + {0x13143, 0x5a1}, > > + {0x1200b2, 0xdc}, > > + {0x110043, 0x5a1}, > > + {0x110143, 0x5a1}, > > + {0x111043, 0x5a1}, > > + {0x111143, 0x5a1}, > > + {0x112043, 0x5a1}, > > + {0x112143, 0x5a1}, > > + {0x113043, 0x5a1}, > > + {0x113143, 0x5a1}, > > + {0x2200b2, 0xdc}, > > + {0x210043, 0x5a1}, > > + {0x210143, 0x5a1}, > > + {0x211043, 0x5a1}, > > + {0x211143, 0x5a1}, > > + {0x212043, 0x5a1}, > > + {0x212143, 0x5a1}, > > + {0x213043, 0x5a1}, > > + {0x213143, 0x5a1}, > > + {0x200fa, 0x1}, > > + {0x1200fa, 0x1}, > > + {0x2200fa, 0x1}, > > + {0x20019, 0x1}, > > + {0x120019, 0x1}, > > + {0x220019, 0x1}, > > + {0x200f0, 0x660}, > > + {0x200f1, 0x0}, > > + {0x200f2, 0x4444}, > > + {0x200f3, 0x8888}, > > + {0x200f4, 0x5665}, > > + {0x200f5, 0x0}, > > + {0x200f6, 0x0}, > > + {0x200f7, 0xf000}, > > + {0x20025, 0x0}, > > + {0x2002d, 0x0}, > > + {0x12002d, 0x0}, > > + {0x22002d, 0x0}, > > + {0x200c7, 0x21}, > > + {0x1200c7, 0x21}, > > + {0x2200c7, 0x21}, > > + {0x200ca, 0x24}, > > + {0x1200ca, 0x24}, > > + {0x2200ca, 0x24}, > > +}; > > + > > +/* ddr phy trained csr */ > > +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { > > + {0x200b2, 0x0}, > > + {0x1200b2, 0x0}, > > + {0x2200b2, 0x0}, > > + {0x200cb, 0x0}, > > + {0x10043, 0x0}, > > + {0x110043, 0x0}, > > + {0x210043, 0x0}, > > + {0x10143, 0x0}, > > + {0x110143, 0x0}, > > + {0x210143, 0x0}, > > + {0x11043, 0x0}, > > + {0x111043, 0x0}, > > + {0x211043, 0x0}, > > + {0x11143, 0x0}, > > + {0x111143, 0x0}, > > + {0x211143, 0x0}, > > + {0x12043, 0x0}, > > + {0x112043, 0x0}, > > + {0x212043, 0x0}, > > + {0x12143, 0x0}, > > + {0x112143, 0x0}, > > + {0x212143, 0x0}, > > + {0x13043, 0x0}, > > + {0x113043, 0x0}, > > +
