Thanks Weijie,
I made the changes You suggested.
I have also seen You sent a new version of Your patches.
Since mine are based on yours I *think* I should suspend
sending my VoCore2 patches till Yours are fixed and integrated
into master.
@Stefan Roese: is this the right course of action?
I am happy what I have (pending further test, of course!),
but I want this integrated in upstream master, if possible,
so I'm prepared to rebase my patches after Weijie ones
are in.
Any comment welcome.
Side Question: Stefan wrote:
> Most of this can be done by using the
> RAM version now (again). There is no additional RAM booting target now
> any more. You can use the normal U-Boot image for this now. Please note
> the changes TEXT_BASE here. Its now 0x80200000.
This actually seems to work right if I start from my original u-boot
(1.1.3,
flashed at start of SPI NOR), but it fails if I start from a flashed (at the
same location) u-boot-mtmips.bin
I *think* this happens because unpacking actually writes u-boot at
0x80200000 and runs it from there, so "load usb 0:1 80200000 u-boot.bin"
(or equivalent) will overwrite the running u-boot and the following
"go ${fileaddr}" fails:
## Starting application at 0x80200000 ...
<DEAD>
Note that if I load the same version flashed it works ok (presumably because
I'm overwriting with the same content, so no harm done).
How can I load in RAM end test a new version once I flash new-style u-boot?
I am thinking about relinking at a different address, but I'm unsure.
TiA!
Regards
Mauro Condarelli
On 1/21/20 4:11 AM, Weijie Gao wrote:
> On Tue, 2020-01-21 at 00:55 +0100, Mauro Condarelli wrote:
>> Hi Weijie,
>> I attach my, apparently working, port to VoCore2 SoM.
>>
>> These patchsets are on top of Your 21 patch rewrite of MT7628 board,
>>
>> While the first patchset is relatively straightforward, but does not include
>> MMC handling, to enable it I had to backport from Linux Kernel several
>> pieces, essentially clock and interrupt handling.
> You are using a superseded patch series (v1) I submitted several months
> ago. These patches have already been replaced by v3 and merged into the
> mainline.
>
> * "mtmips-clk-gate" from v1 is replaced by "mediatek,mt7628-clk" and the
> function of "mediatek,mt7628-clk" is a superset of "mtmips-clk-gate".
> * The node "intc" has no use at all. U-Boot for mips use no interrupts.
> * mmc property "hclk" is the gating clock of the SD controller module.
> Using <&clk48m> in the v1 patches was a bad idea. I changed it to
> <&clkctrl CLK_SDXC> in v3 to make sure its clock will be always
> enabled.
> * Please move pinctrl properties to your board's dts file.
> * pinctrl name "state_uhs" is not used by mtk-sd in U-Boot. MT7628 does
> not support UHS. You should remove it.
> * vmmc-supply and vqmmc-supply are not used by mtk-sd in U-Boot because
> UHS support is not added to the driver. Besides you have assigned
> wrong values to them. You should remove it.
>
>> Those drivers appear written by You.
>> I am unsure if this is really needed or if there is some other (perhaps
>> cleaner)
>> way to enable MMC.
>>
>> As said this seems to work for me, but I would like to contribute this
>> board upstream, in the best possible way.
>>
>> Please let me know how I should proceed.
> I don't have a board with the "sd_iot_mode" pinmux for SDXC, so I can't
> tell you why you can't use it with my v3 patches. But I have tested v3
> patches on boards using "sd_router_mode" pinmux and they do work well.
>
>> Best Regards and Thanks in Advance
>>
>>
>From 4f09ebe1843b5ccdf9b0edb79be6a5110425df04 Mon Sep 17 00:00:00 2001
From: Mauro Condarelli <[email protected]>
Date: Tue, 21 Jan 2020 00:37:43 +0100
Subject: [PATCH] mips: mtmips: vocore2: add support for MMC/SD
Signed-off-by: Mauro Condarelli <[email protected]>
---
arch/mips/dts/mt7628a.dtsi | 18 ++++++++++++++++++
arch/mips/dts/vocore_vocore2.dts | 4 ++++
configs/vocore2_defconfig | 10 +++++++++-
drivers/phy/Kconfig | 2 ++
include/configs/vocore2.h | 22 +++++++++++-----------
5 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi
index f265cb6ad9..5e396e15f4 100644
--- a/arch/mips/dts/mt7628a.dtsi
+++ b/arch/mips/dts/mt7628a.dtsi
@@ -7,6 +7,18 @@
#size-cells = <1>;
compatible = "ralink,mt7628a-soc";
+ resetc: reset-controller {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
clk48m: clk48m@0 {
compatible = "fixed-clock";
@@ -41,6 +53,12 @@
u-boot,dm-pre-reloc;
};
+ clkgate: clkgate@0x30 {
+ reg = <0x30 0x4>;
+ compatible = "mediatek,mediatek,mt7628-clk";
+ #clock-cells = <1>;
+ };
+
rstctrl: rstctrl@0x34 {
reg = <0x34 0x4>;
compatible = "mediatek,mtmips-reset";
diff --git a/arch/mips/dts/vocore_vocore2.dts b/arch/mips/dts/vocore_vocore2.dts
index ec9df70f55..f7450a9687 100644
--- a/arch/mips/dts/vocore_vocore2.dts
+++ b/arch/mips/dts/vocore_vocore2.dts
@@ -61,4 +61,8 @@
&mmc {
status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_iot_mode>;
+ pinctrl-1 = <&sd_iot_mode>;
};
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
index 6cc85ae64a..9758038dd7 100644
--- a/configs/vocore2_defconfig
+++ b/configs/vocore2_defconfig
@@ -28,10 +28,12 @@ CONFIG_CMD_LICENSE=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
@@ -43,10 +45,13 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_SPL_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
-CONFIG_BLK=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_MMC_HW_PARTITIONING is not set
+CONFIG_MMC_MTK=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -57,6 +62,7 @@ CONFIG_SPI_FLASH_MTD=y
# CONFIG_DM_ETH is not set
CONFIG_PHY=y
CONFIG_MT76X8_USB_PHY=y
+# CONFIG_RAM_ROCKCHIP_DEBUG is not set
CONFIG_SPI=y
CONFIG_MT7621_SPI=y
CONFIG_USB=y
@@ -64,6 +70,8 @@ CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
+CONFIG_WDT=y
+CONFIG_WDT_MT7621=y
CONFIG_FS_EXT4=y
CONFIG_LZMA=y
CONFIG_LZO=y
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a72f34f0d4..d9acda2c6a 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -201,6 +201,8 @@ config MT76X8_USB_PHY
bool "MediaTek MT76x8 (7628/88) USB PHY support"
depends on PHY
depends on SOC_MT7628
+ select CLK
+ select DM_RESET
help
Support the USB PHY in MT76x8 SoCs
diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h
index e90c3c2d74..8006cf8804 100644
--- a/include/configs/vocore2.h
+++ b/include/configs/vocore2.h
@@ -7,14 +7,14 @@
#define __VOCORE2_CONFIG_H__
/* CPU */
-#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
+#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000)
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -42,17 +42,17 @@
230400, 460800, 921600 }
/* RAM */
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x80400000
+#define CONFIG_SYS_MEMTEST_START 0x80100000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
/* Memory usage */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
-#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#define CONFIG_SYS_CBSIZE 512
/* U-Boot */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* Environment settings */
#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
--
2.25.0
