Re: [U-Boot] [PATCH] ARM: socfpga: Remove socfpga_sdram_apply_static_cfg()

[Nico Becker]

Am 06.02.2020 um 12:53 schrieb Marek Vasut:
On 2/6/20 11:50 AM, Nico Becker wrote:
Hello,

Hi,

after removing the function socfpga_sdram_apply_static_cfg() in
misc_gen5 we can not use the FPGA2SDRAM bridge.

Without the apply static cfg the kernel crash every time,
if we try to write @ the fpga2sdram bridge. After an soft reset
everything is working.

If we add the socfpga_sdram_apply_static_cfg() in the
u-boot source code, everything is fine.
Now we can use the fpga2sdram bridge after power on.

Our setup:
- u-boot v2020.01
   - load and write fpga firmware
   - enable bridges
- boot linux

I have found some information at
<https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge>

<http://u-boot.10912.n7.nabble.com/WG-Linux-hang-td314276.html>

Can you send a patch which fixes this for you, with Fixes: tag ?
Then it would be clear what you changed.

Thanks


Hello,
the code was removed @ commit c5f4b805.

I attached my patch, sorry for the format, i am new in this.

Thanks a lot

---
 arch/arm/mach-socfpga/misc_gen5.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc_gen5.c 
b/arch/arm/mach-socfpga/misc_gen5.c
index 22042d0de0..19c6d24170 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -213,6 +213,35 @@ static struct socfpga_reset_manager 
*reset_manager_base =
 static struct socfpga_sdr_ctrl *sdr_ctrl =
        (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

+static void socfpga_sdram_apply_static_cfg(void)
+{
+       const u32 applymask = 0x8;
+       u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
+
+       /*
+        * SDRAM staticcfg register specific:
+        * When applying the register setting, the CPU must not access
+        * SDRAM. Luckily for us, we can abuse i-cache here to help us
+        * circumvent the SDRAM access issue. The idea is to make sure
+        * that the code is in one full i-cache line by branching past
+        * it and back. Once it is in the i-cache, we execute the core
+        * of the code and apply the register settings.
+        *
+        * The code below uses 7 instructions, while the Cortex-A9 has
+        * 32-byte cachelines, thus the limit is 8 instructions total.
+        */
+       asm volatile(
+               ".align    5                       \n"
+               "  b       2f              \n"
+               "1:        str     %0,     [%1]    \n"
+               "  dsb                     \n"
+               "  isb                     \n"
+               "  b       3f              \n"
+               "2:        b       1b              \n"
+               "3:        nop                     \n"
+       : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
+}
+
 void do_bridge_reset(int enable, unsigned int mask)
 {
        int i;
@@ -227,6 +256,7 @@ void do_bridge_reset(int enable, unsigned int mask)
                }

                writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+               socfpga_sdram_apply_static_cfg();
                writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
                writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
                writel(iswgrp_handoff[1], &nic301_regs->remap);
@@ -236,6 +266,7 @@ void do_bridge_reset(int enable, unsigned int mask)
        } else {
                writel(0, &sysmgr_regs->fpgaintfgrp_module);
                writel(0, &sdr_ctrl->fpgaport_rst);
+               socfpga_sdram_apply_static_cfg();
                writel(0x7, &reset_manager_base->brg_mod_reset);
                writel(1, &nic301_regs->remap);
        }
--
2.20.1