Add missing L2 cache entry in dts to avoid warning during Linux
kernel boot.
Signed-off-by: Loic Devulder <ldevul...@suse.com>
---
arch/arm/dts/rk3328.dtsi | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 060c84e6c0..7334eb124d 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -38,7 +38,10 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
-// clocks = <&cru ARMCLK>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
@@ -46,19 +49,39 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ next-level-cache = <&l2>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+
};
cpu0_opp_table: opp_table0 {
--
2.25.0
