Hi,
> From: U-Boot <[email protected]> On Behalf Of Pragnesh Patel
> Sent: lundi 24 février 2020 09:33
>
> Added a misc driver to handle OTP memory in SiFive SoCs.
>
> Signed-off-by: Pragnesh Patel <[email protected]>
> ---
> drivers/misc/Kconfig | 7 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/sifive-otp.c | 241 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 249 insertions(+)
> create mode 100644 drivers/misc/sifive-otp.c
>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> f18aa8f7ba..fcb45c63d4 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -68,6 +68,13 @@ config ROCKCHIP_OTP
> addressing and a length or through child-nodes that are generated
> based on the e-fuse map retrieved from the DTS.
>
> +config SIFIVE_OTP
> + bool "SiFive Ememory OTP driver"
> + depends on RISCV && MISC
> + help
> + Enable support for reading and writing the ememory OTP on the
> + SiFive SoCs.
> +
> config VEXPRESS_CONFIG
> bool "Enable support for Arm Versatile Express config bus"
> depends on MISC
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> 2b843de93c..ee888631b6 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -58,6 +58,7 @@ obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
> obj-$(CONFIG_QFW) += qfw.o
> obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
> obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
> +obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
> obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
> obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
> obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o diff --git
> a/drivers/misc/sifive-otp.c b/drivers/misc/sifive-otp.c new file mode 100644
> index
> 0000000000..6a39ec42df
> --- /dev/null
> +++ b/drivers/misc/sifive-otp.c
> @@ -0,0 +1,241 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This is a driver for the eMemory EG004K32TQ028XW01 NeoFuse
> + * One-Time-Programmable (OTP) memory used within the SiFive FU540.
> + * It is documented in the FU540 manual here:
> + * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
> + *
> + * Copyright (C) 2018 Philipp Hug <[email protected]>
> + * Copyright (C) 2018 Joey Hewitt <[email protected]>
> + *
> + * Copyright (C) 2020 SiFive, Inc
> + */
> +
> +/*
> + * The FU540 stores 4096x32 bit (16KiB) values.
> + * Index 0x00-0xff are reserved for SiFive internal use. (first 1KiB)
> + * Right now first 1KB is used to store only serial number.
> + */
> +
> +#include <common.h>
> +#include <dm/device.h>
> +#include <dm/read.h>
> +#include <linux/io.h>
> +#include <misc.h>
> +
> +#define BYTES_PER_FUSE 4
> +
> +#define PA_RESET_VAL 0x00
> +#define PAS_RESET_VAL 0x00
> +#define PAIO_RESET_VAL 0x00
> +#define PDIN_RESET_VAL 0x00
> +#define PTM_RESET_VAL 0x00
> +
> +#define PCLK_ENABLE_VAL BIT(0)
> +#define PCLK_DISABLE_VAL 0x00
> +
> +#define PWE_WRITE_ENABLE BIT(0)
> +#define PWE_WRITE_DISABLE 0x00
> +
> +#define PTM_FUSE_PROGRAM_VAL BIT(1)
> +
> +#define PCE_ENABLE_INPUT BIT(0)
> +#define PCE_DISABLE_INPUT 0x00
> +
> +#define PPROG_ENABLE_INPUT BIT(0)
> +#define PPROG_DISABLE_INPUT 0x00
> +
> +#define PTRIM_ENABLE_INPUT BIT(0)
> +#define PTRIM_DISABLE_INPUT 0x00
> +
> +#define PDSTB_DEEP_STANDBY_ENABLE BIT(0)
> +#define PDSTB_DEEP_STANDBY_DISABLE 0x00
> +
> +struct sifive_otp_regs {
> + u32 pa; /* Address input */
> + u32 paio; /* Program address input */
> + u32 pas; /* Program redundancy cell selection input */
> + u32 pce; /* OTP Macro enable input */
> + u32 pclk; /* Clock input */
> + u32 pdin; /* Write data input */
> + u32 pdout; /* Read data output */
> + u32 pdstb; /* Deep standby mode enable input (active low) */
> + u32 pprog; /* Program mode enable input */
> + u32 ptc; /* Test column enable input */
> + u32 ptm; /* Test mode enable input */
> + u32 ptm_rep;/* Repair function test mode enable input */
> + u32 ptr; /* Test row enable input */
> + u32 ptrim; /* Repair function enable input */
> + u32 pwe; /* Write enable input (defines program cycle) */
> +} __packed;
> +
> +struct sifive_otp_platdata {
> + struct sifive_otp_regs __iomem *regs;
> + u32 total_fuses;
> +};
> +
> +/*
> + * offset and size are assumed aligned to the size of the fuses (32bit).
> + */
> +static int sifive_otp_read(struct udevice *dev, int offset,
> + void *buf, int size)
> +{
> + struct sifive_otp_platdata *plat = dev_get_platdata(dev);
> + struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
> +
> + int fuseidx = offset / BYTES_PER_FUSE;
> + int fusecount = size / BYTES_PER_FUSE;
> + u32 fusebuf[fusecount];
> +
> + /* check bounds */
> + if (offset < 0 || size < 0)
> + return -EINVAL;
> + if (fuseidx >= plat->total_fuses)
> + return -EINVAL;
> + if ((fuseidx + fusecount) > plat->total_fuses)
> + return -EINVAL;
> +
> + /* init OTP */
> + iowrite32(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
> + iowrite32(PTRIM_ENABLE_INPUT, ®s->ptrim);
> + iowrite32(PCE_ENABLE_INPUT, ®s->pce);
> +
> + /* read all requested fuses */
> + for (unsigned int i = 0; i < fusecount; i++, fuseidx++) {
> + iowrite32(fuseidx, ®s->pa);
> +
> + /* cycle clock to read */
> + iowrite32(PCLK_ENABLE_VAL, ®s->pclk);
> + mdelay(1);
> + iowrite32(PCLK_DISABLE_VAL, ®s->pclk);
> + mdelay(1);
> +
> + /* read the value */
> + fusebuf[i] = ioread32(®s->pdout);
> + }
> +
> + /* shut down */
> + iowrite32(PCE_DISABLE_INPUT, ®s->pce);
> + iowrite32(PTRIM_DISABLE_INPUT, ®s->ptrim);
> + iowrite32(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
> +
> + // copy out
> + memcpy(buf, fusebuf, size);
> +
> + return 0;
Since the commit 8729b1ae2cbd ("misc: Update read() and write() methods to
return bytes xfered")
return size;
> +}
> +
> +/*
> + * Caution:
> + * OTP can be written only once, so use carefully.
> + *
> + * offset and size are assumed aligned to the size of the fuses (32bit).
> + */
> +static int sifive_otp_write(struct udevice *dev, int offset,
> + const void *buf, int size)
> +{
> + struct sifive_otp_platdata *plat = dev_get_platdata(dev);
> + struct sifive_otp_regs *regs = (struct sifive_otp_regs *)plat->regs;
> +
> + int fuseidx = offset / BYTES_PER_FUSE;
> + int fusecount = size / BYTES_PER_FUSE;
> + u32 *write_buf = (u32 *)buf;
> + u32 write_data;
> + int i, pas, bit;
> +
> + /* check bounds */
> + if (offset < 0 || size < 0)
> + return -EINVAL;
> + if (fuseidx >= plat->total_fuses)
> + return -EINVAL;
> + if ((fuseidx + fusecount) > plat->total_fuses)
> + return -EINVAL;
> +
> + /* init OTP */
> + iowrite32(PDSTB_DEEP_STANDBY_ENABLE, ®s->pdstb);
> + iowrite32(PTRIM_ENABLE_INPUT, ®s->ptrim);
> +
> + /* reset registers */
> + iowrite32(PCLK_DISABLE_VAL, ®s->pclk);
> + iowrite32(PA_RESET_VAL, ®s->pa);
> + iowrite32(PAS_RESET_VAL, ®s->pas);
> + iowrite32(PAIO_RESET_VAL, ®s->paio);
> + iowrite32(PDIN_RESET_VAL, ®s->pdin);
> + iowrite32(PWE_WRITE_DISABLE, ®s->pwe);
> + iowrite32(PTM_FUSE_PROGRAM_VAL, ®s->ptm);
> + mdelay(1);
> +
> + iowrite32(PCE_ENABLE_INPUT, ®s->pce);
> + iowrite32(PPROG_ENABLE_INPUT, ®s->pprog);
> + iowrite32(PTRIM_ENABLE_INPUT, ®s->ptrim);
> +
> + /* write all requested fuses */
> + for (i = 0; i < fusecount; i++, fuseidx++) {
> + iowrite32(fuseidx, ®s->pa);
> + write_data = *(write_buf++);
> +
> + for (pas = 0; pas < 2; pas++) {
> + iowrite32(pas, ®s->pas);
> +
> + for (bit = 0; bit < 32; bit++) {
> + iowrite32(bit, ®s->paio);
> + iowrite32(((write_data >> bit) & 1),
> + ®s->pdin);
> + mdelay(1);
> +
> + iowrite32(PWE_WRITE_ENABLE, ®s->pwe);
> + mdelay(1);
> + iowrite32(PWE_WRITE_DISABLE, ®s->pwe);
> + mdelay(1);
> + }
> + }
> +
> + iowrite32(PAS_RESET_VAL, ®s->pas);
> + }
> +
> + /* shut down */
> + iowrite32(PWE_WRITE_DISABLE, ®s->pwe);
> + iowrite32(PPROG_DISABLE_INPUT, ®s->pprog);
> + iowrite32(PCE_DISABLE_INPUT, ®s->pce);
> + iowrite32(PTM_RESET_VAL, ®s->ptm);
> +
> + iowrite32(PTRIM_DISABLE_INPUT, ®s->ptrim);
> + iowrite32(PDSTB_DEEP_STANDBY_DISABLE, ®s->pdstb);
> +
> + return 0;
Since the commit 8729b1ae2cbd ("misc: Update read() and write() methods to
return bytes xfered")
return size;
> +}
> +
> +static int sifive_otp_ofdata_to_platdata(struct udevice *dev) {
> + struct sifive_otp_platdata *plat = dev_get_platdata(dev);
> + int ret;
> +
> + plat->regs = dev_read_addr_ptr(dev);
> +
> + ret = dev_read_u32(dev, "fuse-count", &plat->total_fuses);
> + if (ret < 0) {
> + pr_err("\"fuse-count\" not found\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct misc_ops sifive_otp_ops = {
> + .read = sifive_otp_read,
> + .write = sifive_otp_write,
> +};
> +
> +static const struct udevice_id sifive_otp_ids[] = {
> + { .compatible = "sifive,fu540-otp" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(sifive_otp) = {
> + .name = "sifive_otp",
> + .id = UCLASS_MISC,
> + .of_match = sifive_otp_ids,
> + .ofdata_to_platdata = sifive_otp_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct sifive_otp_platdata),
> + .ops = &sifive_otp_ops,
> +};
> --
> 2.17.1
Regards
Patrick
