Hi Bin, > -----Original Message----- > From: Bin Meng <[email protected]> > Sent: Thursday, February 27, 2020 9:27 PM > To: Park, Aiden <[email protected]> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; u- > [email protected] > Subject: Re: [PATCH] x86: Cache write back at 32-bit entry point > > Hi Aiden, > > On Fri, Feb 28, 2020 at 12:54 PM Park, Aiden <[email protected]> wrote: > > > > In a certain condition, invd causes cache coherence issue. > > 1. Pre-stage boot code passes memory address to U-Boot > > 2. The data of the memory address is still in data cache line > > 3. The invd marks data cache line as invalid without write back > > 4. U-Boot accesses the memory address > > 5. Data is invalid > > > > Therefore, wbinvd is recommended at the 32-bit entry point even though > > it consumes extra cpu clock cycles. > > > > Signed-off-by: Aiden Park <[email protected]> > > --- > > arch/x86/cpu/start.S | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > This is already fixed (reverted) in the x86 tree. Would you please double > check? > Thank you for letting me know that. I think I missed some emails. Thanks again. Andy, appreciate your commit. I had the same issue on Slim Bootloader due to this cache coherence.
> Regards, > Bin Best Regards, Aiden
