On Thu, Dec 5, 2019 at 5:04 PM Michael Walle <mich...@walle.cc> wrote: > > Add support for configuring the CLK_25M pin as well as the RGMII I/O > voltage by the device tree. > > By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. > But this output can also be changed by software to other frequencies. > This commit introduces a generic way to configure this output. > > Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. > An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V > option needs an external supply voltage. This commit adds support to > switch the internal LDO to 1.8V. > > Signed-off-by: Michael Walle <mich...@walle.cc>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
