[PATCH v4 17/21] arm: socfpga: stratix10: Initialize timer in SPL

[chee . hong . ang]

From: Chee Hong Ang <chee.hong....@intel.com>

Initialize timer in SPL running in secure mode (EL3)
and skip timer initialization in U-Boot proper running in
non-secure mode (EL2).

Signed-off-by: Chee Hong Ang <chee.hong....@intel.com>
---
 arch/arm/mach-socfpga/timer_s10.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/timer_s10.c 
b/arch/arm/mach-socfpga/timer_s10.c
index 5723789..0fa56c3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -13,6 +13,7 @@
  */
 int timer_init(void)
 {
+#ifdef CONFIG_SPL_BUILD
        int enable = 0x3;       /* timer enable + output signal masked */
        int loadval = ~0;
 
@@ -21,6 +22,6 @@ int timer_init(void)
        /* enable processor pysical counter */
        asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
        asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
        return 0;
 }
-- 
2.7.4