On 3/9/20 2:59 PM, Patrick Delaunay wrote: > Add clock support for SPI5, as this instance is available on extension > connector of ST board. > > Signed-off-by: Patrick Delaunay <patrick.delau...@st.com> > --- > > drivers/clk/clk_stm32mp1.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c > index 42f9ef4e46..52bd8e96f3 100644 > --- a/drivers/clk/clk_stm32mp1.c > +++ b/drivers/clk/clk_stm32mp1.c > @@ -95,6 +95,7 @@ DECLARE_GLOBAL_DATA_PTR; > #define RCC_I2C12CKSELR 0x8C0 > #define RCC_I2C35CKSELR 0x8C4 > #define RCC_SPI2S1CKSELR 0x8D8 > +#define RCC_SPI45CKSELR 0x8E0 > #define RCC_UART6CKSELR 0x8E4 > #define RCC_UART24CKSELR 0x8E8 > #define RCC_UART35CKSELR 0x8EC > @@ -304,6 +305,7 @@ enum stm32mp1_parent_sel { > _DSI_SEL, > _ADC12_SEL, > _SPI1_SEL, > + _SPI45_SEL, > _RTC_SEL, > _PARENT_SEL_NB, > _UNKNOWN_SEL = 0xff, > @@ -527,6 +529,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] > = { > STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), > > STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL), > + STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL), > STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), > > STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3), > @@ -603,6 +606,8 @@ static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P}; > static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q}; > static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER, > _PLL3_R}; > +static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, > + _HSE_KER}; > static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE}; > > static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { > @@ -629,6 +634,7 @@ static const struct stm32mp1_clk_sel > stm32mp1_clk_sel[_PARENT_SEL_NB] = { > STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents), > STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents), > STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents), > + STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents), > STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT, > (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT), > rtc_parents), > @@ -747,6 +753,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] > = { > [_DSI_SEL] = "DSI", > [_ADC12_SEL] = "ADC12", > [_SPI1_SEL] = "SPI1", > + [_SPI45_SEL] = "SPI45", > [_RTC_SEL] = "RTC", > }; >
Acked-by: Patrice Chotard <patrice.chot...@st.com> Thanks Patrice