Move FSP-M configuration to the device-tree like it's already done for other SoCs (Baytaril).
Signed-off-by: Bernhard Messerklinger <[email protected]> --- arch/x86/cpu/apollolake/fsp_m.c | 337 +++++++++++------- arch/x86/dts/chromebook_coral.dts | 35 ++ .../asm/arch-apollolake/fsp/fsp_m_upd.h | 162 +++++++++ 3 files changed, 414 insertions(+), 120 deletions(-) diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index 5308af8ed4..ee84231acb 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -12,21 +12,6 @@ #include <asm/fsp2/fsp_internal.h> #include <dm/uclass-internal.h> -/* - * ODT settings: - * If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B, - * choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A - * and LOW for ODT_B, choose ODT_A_B_HIGH_LOW. - * - * Note that the enum values correspond to the interpreted UPD fields - * within Ch[3:0]_OdtConfig parameters. - */ -enum { - ODT_A_B_HIGH_LOW = 0 << 1, - ODT_A_B_HIGH_HIGH = 1 << 1, - N_WR_24 = 1 << 5, -}; - /* * LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation. * There are four physical LPDDR4 channels, each 32-bits wide. There are two @@ -67,122 +52,234 @@ struct lpddr4_swizzle_cfg { struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS]; }; -static void setup_sdram(struct fsp_m_config *cfg, - const struct lpddr4_swizzle_cfg *swizzle_cfg) -{ - const struct lpddr4_chan_swizzle_cfg *sch; - /* Number of bytes to copy per DQS */ - const size_t sz = DQ_BITS_PER_DQS; - int chan; - - cfg->memory_down = 1; - cfg->scrambler_support = 1; - cfg->channel_hash_mask = 0x36; - cfg->slice_hash_mask = 9; - cfg->interleaved_mode = 2; - cfg->channels_slices_enable = 0; - cfg->min_ref_rate2x_enable = 0; - cfg->dual_rank_support_enable = 1; - - /* LPDDR4 is memory down so no SPD addresses */ - cfg->dimm0_spd_address = 0; - cfg->dimm1_spd_address = 0; - - for (chan = 0; chan < 4; chan++) { - struct fsp_ram_channel *ch = &cfg->chan[chan]; - - ch->rank_enable = 1; - ch->device_width = 1; - ch->dram_density = 2; - ch->option = 3; - ch->odt_config = ODT_A_B_HIGH_HIGH; - } - - /* - * CH0_DQB byte lanes in the bit swizzle configuration field are - * not 1:1. The mapping within the swizzling field is: - * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] - * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] - * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] - * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; - memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; - memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); - - sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; - memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); - memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); - - /* - * CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. - */ - sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; - memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); - memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); - memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); - memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); -} - int fspm_update_config(struct udevice *dev, struct fspm_upd *upd) { struct fsp_m_config *cfg = &upd->config; struct fspm_arch_upd *arch = &upd->arch; + char chx_buf[30]; + const struct lpddr4_chan_swizzle_cfg *sch; + const struct lpddr4_swizzle_cfg *swizzle_cfg; + const size_t sz = DQ_BITS_PER_DQS; + bool tmp; + const u8 *gpio_table_pins; + const char *oem_file; arch->nvs_buffer_ptr = NULL; prepare_mrc_cache(upd); arch->stack_base = (void *)0xfef96000; arch->boot_loader_tolum_size = 0; - arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION; - cfg->serial_debug_port_type = 2; - cfg->serial_debug_port_device = 2; - cfg->serial_debug_port_stride_size = 2; - cfg->serial_debug_port_address = 0; - - cfg->package = 1; - /* Don't enforce a memory size limit */ - cfg->memory_size_limit = 0; - cfg->low_memory_max_value = 2048; /* 2 GB */ - /* No restrictions on memory above 4GiB */ - cfg->high_memory_max_value = 0; - - /* Always default to attempt to use saved training data */ - cfg->disable_fast_boot = 0; - - const u8 *swizzle_data; - - swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle", - LP4_NUM_BYTE_LANES * - DQ_BITS_PER_DQS * - LP4_NUM_PHYS_CHANNELS); - if (!swizzle_data) - return log_msg_ret("Cannot read swizzel data", -EINVAL); - - setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data); - - cfg->pre_mem_gpio_table_ptr = 0; - cfg->profile = 0xb; - cfg->msg_level_mask = 0; - - /* other */ - cfg->skip_cse_rbp = 1; - cfg->periodic_retraining_disable = 0; - cfg->enable_s3_heci2 = 0; + cfg->serial_debug_port_type = dev_read_u32_default(dev, + "fspm,serial-debug-port-type", + SERIAL_DEBUG_PORT_TYPE_MMIO); + cfg->serial_debug_port_device = dev_read_u32_default(dev, + "fspm,serial-debug-port-device", + SERIAL_DEBUG_PORT_DEVICE_UART2); + if (cfg->serial_debug_port_device == SERIAL_DEBUG_PORT_DEVICE_EXTERNAL) + cfg->serial_debug_port_address = dev_read_u32_default(dev, + "fspm,serial-debug-port-address", + 0); + cfg->serial_debug_port_stride_size = dev_read_u32_default(dev, + "fspm,serial-debug-port-stride-size", + SERIAL_DEBUG_PORT_STRIDE_SIZE_4); + cfg->mrc_fast_boot = !dev_read_bool(dev, "fspm,disable-mrc-fast-boot"); + cfg->igd = !dev_read_bool(dev, "fspm,disable-igd"); + if (cfg->igd) { + cfg->igd_dvmt50_pre_alloc = dev_read_u32_default(dev, + "fspm,igd-dvmt50-pre-alloc", + IGD_DVMT_50_PRE_ALLOC_64M); + cfg->igd_aperture_size = dev_read_u32_default(dev, + "fspm,aperture-size", + IGD_APERTURE_SIZE_128M); + cfg->gtt_size = dev_read_u32_default(dev, "fspm,gtt-size", + GTT_SIZE_8M); + cfg->primary_video_adaptor = dev_read_u32_default(dev, + "fspm,primary-video-adaptor", + PRIMARY_VIDEO_ADAPTER_AUTO); + } + cfg->package = dev_read_u32_default(dev, "fspm,package", + PACKAGE_SODIMM); + cfg->profile = dev_read_u32_default(dev, "fspm,profile", + PROFILE_DDR3_1600_11_11_11); + cfg->memory_down = dev_read_u32_default(dev, "fspm,memory-down", + MEMORY_DOWN_NO); + if (cfg->memory_down & MEMORY_DOWN_YES) { + cfg->ddr3_l_page_size = dev_read_u32_default(dev, + "fspm,ddr3l-page-size", 1); + cfg->ddr3_lasr = dev_read_bool(dev, "fspm,enable-ddr3-lasr"); + } + cfg->scrambler_support = dev_read_bool(dev, + "fspm,enable-scrambler-support"); + tmp = dev_read_bool(dev, "enable-interleaved-mode"); + cfg->interleaved_mode = (tmp == 0) ? INTERLEAVED_MODE_DISABLE : + INTERLEAVED_MODE_ENABLE; + cfg->channel_hash_mask = dev_read_u32_default(dev, + "fspm,channel-hash-mask", + 0); + cfg->slice_hash_mask = dev_read_u32_default(dev, + "fspm,slice-hash-mask", 0); + cfg->channels_slices_enable = dev_read_bool(dev, + "fspm,enable-channels-slices"); + cfg->min_ref_rate2x_enable = dev_read_bool(dev, + "fspm,enable-min-ref-rate2x"); + cfg->dual_rank_support_enable = !dev_read_bool(dev, + "fspm,disable-dual-rank-support"); + tmp = dev_read_bool(dev, "fspm,enable-rmt-mode"); + cfg->rmt_mode = (tmp == 0) ? RMT_MODE_DISABLE : RMT_MODE_ENABLE; + cfg->memory_size_limit = dev_read_u32_default(dev, + "fspm,memory-size-limit", 0); + cfg->low_memory_max_value = dev_read_u32_default(dev, + "fspm,low-memory-max-value", 0); + cfg->high_memory_max_value = dev_read_u32_default(dev, + "fspm,high-memory-max-value", + 0); + cfg->disable_fast_boot = dev_read_bool(dev, "fspm,disable-fast-boot"); + cfg->dimm0_spd_address = 0; + cfg->dimm1_spd_address = 0; + if (!(cfg->memory_down & MEMORY_DOWN_YES)) { + cfg->dimm0_spd_address = dev_read_u32_default(dev, + "fspm,dimm0-spd-address", 0xa0); + cfg->dimm1_spd_address = dev_read_u32_default(dev, + "fspm,dimm1-spd-address", 0xa4); + } + if (cfg->memory_down != 0) { + for (int i = 0; i < FSP_DRAM_CHANNELS; i++) { + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-enable-rank", i); + cfg->chan[i].rank_enable = dev_read_bool(dev, chx_buf); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-device-width", i); + cfg->chan[i].device_width = dev_read_u32_default(dev, + chx_buf, 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-dram-density", i); + cfg->chan[i].dram_density = dev_read_u32_default(dev, + chx_buf, 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-option", i); + cfg->chan[i].option = dev_read_u32_default(dev, chx_buf, + 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-odt-config", i); + cfg->chan[i].odt_config = dev_read_u32_default(dev, + chx_buf, + 0); + cfg->chan[i].tristate_clk1 = 0; + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-enable-mode2-n", i); + cfg->chan[i].mode2_n = dev_read_u32_default(dev, + chx_buf, 0); + snprintf(chx_buf, sizeof(chx_buf), + "fspm,ch%d-odt-levels", i); + cfg->chan[i].odt_levels = dev_read_u32_default(dev, + chx_buf, + CHX_ODT_LEVELS_CONNECTED_TO_SOC); + } + } + cfg->rmt_check_run = dev_read_bool(dev, + "fspm,rmt-degrade-margin-check"); + cfg->rmt_margin_check_scale_high_threshold = dev_read_u32_default(dev, + "fspm,rmt-margin-check-scale-high-threshold", + 0); + swizzle_cfg = (const struct lpddr4_swizzle_cfg *)dev_read_u8_array_ptr( + dev, "lpddr4-swizzle", + LP4_NUM_BYTE_LANES * + DQ_BITS_PER_DQS * + LP4_NUM_PHYS_CHANNELS); + + if (swizzle_cfg) { + /* + * CH0_DQB byte lanes in the bit swizzle configuration field are + * not 1:1. The mapping within the swizzling field is: + * indices [0:7] - byte lane 1 (DQS1) DQ[8:15] + * indices [8:15] - byte lane 0 (DQS0) DQ[0:7] + * indices [16:23] - byte lane 3 (DQS3) DQ[24:31] + * indices [24:31] - byte lane 2 (DQS2) DQ[16:23] + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0B]; + memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz); + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are + * 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH0A]; + memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz); + sch = &swizzle_cfg->phys[LP4_PHYS_CH1B]; + memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz); + memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz); + /* + * CH0_DQA byte lanes in the bit swizzle configuration field are + * 1:1. + */ + sch = &swizzle_cfg->phys[LP4_PHYS_CH1A]; + memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz); + memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz); + memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz); + memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz); + } + cfg->msg_level_mask = dev_read_u32_default(dev, "fspm,msg-level-mask", + 0); + memset(cfg->pre_mem_gpio_table_pin_num, 0, + sizeof(cfg->pre_mem_gpio_table_pin_num)); + gpio_table_pins = dev_read_u8_array_ptr(dev, + "fspm,pre-mem-gpio-table-pin-num", + sizeof(gpio_table_pins)); + if (gpio_table_pins) + memcpy(cfg->pre_mem_gpio_table_pin_num, gpio_table_pins, + sizeof(gpio_table_pins)); + cfg->pre_mem_gpio_table_ptr = dev_read_u32_default(dev, + "fspm,pre-mem-gpio-table-ptr", + 0); + cfg->pre_mem_gpio_table_entry_num = dev_read_u32_default(dev, + "fspm,pre-mem-gpio-table-entry-num", + 0); + cfg->enhance_port8xh_decoding = !dev_read_bool(dev, + "fspm,disable-enhance-port8xh-decoding"); + cfg->spd_write_enable = dev_read_bool(dev, "fspm,enable-spd-write"); + cfg->oem_loading_base = dev_read_u32_default(dev, + "fspm,oem-loading-base", + 0); + memset(cfg->oem_file_name, 0, sizeof(cfg->oem_file_name)); + oem_file = dev_read_string(dev, "oem-file-name"); + if (oem_file) + memcpy(cfg->oem_file_name, oem_file, + sizeof(cfg->oem_file_name)); + cfg->mrc_data_saving = dev_read_bool(dev, + "fspm,enable_mrc-data-saving"); + cfg->e_mmc_trace_len = dev_read_bool(dev, "emmc-trace-len-short"); + cfg->skip_cse_rbp = dev_read_bool(dev, "fspm,enable-skip-cse-rbp"); + cfg->npk_en = dev_read_u32_default(dev, "fspm,enable-npk", NPK_EN_AUTO); + cfg->fw_trace_en = !dev_read_bool(dev, "fspm,disable-fw-trace"); + cfg->fw_trace_destination = dev_read_u32_default(dev, + "fspm,fw-trace-destination", + FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI); + cfg->recover_dump = dev_read_bool(dev, "fspm,enable-recover-dump"); + cfg->msc0_wrap = dev_read_u32_default(dev, "msc0-wrap", MSC_X_WRAP_1); + cfg->msc1_wrap = dev_read_u32_default(dev, "msc1-wrap", MSC_X_WRAP_1); + cfg->msc0_size = dev_read_u32_default(dev, "fspm,msc0-size", + MSC_X_SIZE_0M); + cfg->msc1_size = dev_read_u32_default(dev, "fspm,msc1-size", + MSC_X_SIZE_0M); + cfg->pti_mode = dev_read_u32_default(dev, "fspm,pti-mode", PTI_MODE_x4); + cfg->pti_training = dev_read_u32_default(dev, "fspm,pti-training", 0); + cfg->pti_speed = dev_read_u32_default(dev, "fspm,pti-speed", + PTI_SPEED_QUARTER); + cfg->punit_mlvl = dev_read_u32_default(dev, "fspm,punit-mlvl", 0); + cfg->pmc_mlvl = dev_read_u32_default(dev, "fspm,pmc-mlvl", 0); + cfg->sw_trace_en = dev_read_bool(dev, "fspm,enable-sw-trace"); + cfg->periodic_retraining_disable = dev_read_bool(dev, + "fspm,disable-periodic-retraining"); + cfg->enable_reset_system = dev_read_bool(dev, "enable-reset-system"); + cfg->enable_s3_heci2 = !dev_read_bool(dev, "fspm,disable-s3-heci2"); return 0; } diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index af52e11c89..a205430abf 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -21,6 +21,7 @@ #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> +#include <asm/arch-apollolake/fsp/fsp_m_upd.h> / { model = "Google Coral"; @@ -436,6 +437,40 @@ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; + fspm,package = <PACKAGE_BGA>; + fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; + fspm,memory-down = <MEMORY_DOWN_YES>; + fspm,enable-scrambler-support; + fspm,enable-interleaved-mode = <INTERLEAVED_MODE_ENABLE>; + fspm,channel-hash-mask = <0x36>; + fspm,slice-hash-mask = <0x9>; + fspm,low-memory-max-value = <2048>; + fspm,ch0-enable-rank; + fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch1-enable-rank; + fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch2-enable-rank; + fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,ch3-enable-rank; + fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>; + fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>; + fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING | + CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>; + fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>; + fspm,enable-skip-cse-rbp; + lpddr4-swizzle = /bits/ 8 < /* LP4_PHYS_CH0A */ diff --git a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h index 93bee5b2d1..de7cdacde4 100644 --- a/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h +++ b/arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h @@ -7,6 +7,7 @@ #ifndef __ASM_ARCH_FSP_M_UDP_H #define __ASM_ARCH_FSP_M_UDP_H +#ifndef __ASSEMBLY__ #include <asm/fsp2/fsp_api.h> #define FSP_DRAM_CHANNELS 4 @@ -119,5 +120,166 @@ struct __packed fspm_upd { u8 unused_upd_space2[158]; u16 upd_terminator; }; +#endif + +#define SERIAL_DEBUG_PORT_TYPE_NONE 0 +#define SERIAL_DEBUG_PORT_TYPE_IO 1 +#define SERIAL_DEBUG_PORT_TYPE_MMIO 2 + +#define SERIAL_DEBUG_PORT_DEVICE_UART0 0 +#define SERIAL_DEBUG_PORT_DEVICE_UART1 1 +#define SERIAL_DEBUG_PORT_DEVICE_UART2 2 +#define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3 + +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0 +#define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2 + +#define IGD_DVMT_50_PRE_ALLOC_64M 0x02 +#define IGD_DVMT_50_PRE_ALLOC_96M 0x03 +#define IGD_DVMT_50_PRE_ALLOC_128M 0x04 +#define IGD_DVMT_50_PRE_ALLOC_160M 0x05 +#define IGD_DVMT_50_PRE_ALLOC_192M 0x06 +#define IGD_DVMT_50_PRE_ALLOC_224M 0x07 +#define IGD_DVMT_50_PRE_ALLOC_256M 0x08 +#define IGD_DVMT_50_PRE_ALLOC_288M 0x09 +#define IGD_DVMT_50_PRE_ALLOC_320M 0x0a +#define IGD_DVMT_50_PRE_ALLOC_352M 0x0b +#define IGD_DVMT_50_PRE_ALLOC_384M 0x0c +#define IGD_DVMT_50_PRE_ALLOC_416M 0x0d +#define IGD_DVMT_50_PRE_ALLOC_448M 0x0e +#define IGD_DVMT_50_PRE_ALLOC_480M 0x0f +#define IGD_DVMT_50_PRE_ALLOC_512M 0x10 + +#define IGD_APERTURE_SIZE_128M 0x1 +#define IGD_APERTURE_SIZE_256M 0x2 +#define IGD_APERTURE_SIZE_512M 0x3 + +#define GTT_SIZE_2M 1 +#define GTT_SIZE_4M 2 +#define GTT_SIZE_8M 3 + +#define PRIMARY_VIDEO_ADAPTER_AUTO 0 +#define PRIMARY_VIDEO_ADAPTER_IGD 2 +#define PRIMARY_VIDEO_ADAPTER_PCI 3 + +#define PACKAGE_SODIMM 0 +#define PACKAGE_BGA 1 +#define PACKAGE_BGA_MIRRORED 2 +#define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3 + +#define PROFILE_WIO2_800_7_8_8 0x1 +#define PROFILE_WIO2_1066_9_10_10 0x2 +#define PROFILE_LPDDR3_1066_8_10_10 0x3 +#define PROFILE_LPDDR3_1333_10_12_12 0x4 +#define PROFILE_LPDDR3_1600_12_15_15 0x5 +#define PROFILE_LPDDR3_1866_14_17_17 0x6 +#define PROFILE_LPDDR3_2133_16_20_20 0x7 +#define PROFILE_LPDDR4_1066_10_10_10 0x8 +#define PROFILE_LPDDR4_1600_14_15_15 0x9 +#define PROFILE_LPDDR4_2133_20_20_20 0xa +#define PROFILE_LPDDR4_2400_24_22_22 0xb +#define PROFILE_LPDDR4_2666_24_24_24 0xc +#define PROFILE_LPDDR4_2933_28_27_27 0xd +#define PROFILE_LPDDR4_3200_28_29_29 0xe +#define PROFILE_DDR3_1066_6_6_6 0xf +#define PROFILE_DDR3_1066_7_7_7 0x10 +#define PROFILE_DDR3_1066_8_8_8 0x11 +#define PROFILE_DDR3_1333_7_7_7 0x12 +#define PROFILE_DDR3_1333_8_8_8 0x13 +#define PROFILE_DDR3_1333_9_9_9 0x14 +#define PROFILE_DDR3_1333_10_10_10 0x15 +#define PROFILE_DDR3_1600_8_8_8 0x16 +#define PROFILE_DDR3_1600_9_9_9 0x17 +#define PROFILE_DDR3_1600_10_10_10 0x18 +#define PROFILE_DDR3_1600_11_11_11 0x19 +#define PROFILE_DDR3_1866_10_10_10 0x1a +#define PROFILE_DDR3_1866_11_11_11 0x1b +#define PROFILE_DDR3_1866_12_12_12 0x1c +#define PROFILE_DDR3_1866_13_13_13 0x1d +#define PROFILE_DDR3_2133_11_11_11 0x1e +#define PROFILE_DDR3_2133_12_12_12 0x1f +#define PROFILE_DDR3_2133_13_13_13 0x20 +#define PROFILE_DDR3_2133_14_14_14 0x21 +#define PROFILE_DDR4_1333_10_10_10 0x22 +#define PROFILE_DDR4_1600_10_10_10 0x23 +#define PROFILE_DDR4_1600_11_11_11 0x24 +#define PROFILE_DDR4_1600_12_12_12 0x25 +#define PROFILE_DDR4_1866_12_12_12 0x26 +#define PROFILE_DDR4_1866_13_13_13 0x27 +#define PROFILE_DDR4_1866_14_14_14 0x28 +#define PROFILE_DDR4_2133_14_14_14 0x29 +#define PROFILE_DDR4_2133_15_15_15 0x2a +#define PROFILE_DDR4_2133_16_16_16 0x2b +#define PROFILE_DDR4_2400_15_15_15 0x2c +#define PROFILE_DDR4_2400_16_16_16 0x2d +#define PROFILE_DDR4_2400_17_17_17 0x2e +#define PROFILE_DDR4_2400_18_18_18 0x2f + +#define MEMORY_DOWN_NO 0 +#define MEMORY_DOWN_YES 1 +#define MEMORY_DOWN_MD_SODIMM 2 +#define MEMORY_DOWN_LPDDR4 3 + +#define INTERLEAVED_MODE_DISABLE 0 +#define INTERLEAVED_MODE_ENABLE 2 + +#define RMT_MODE_DISABLE 0 +#define RMT_MODE_ENABLE 3 + +#define CHX_DEVICE_WIDTH_X8 0 +#define CHX_DEVICE_WIDTH_X16 1 +#define CHX_DEVICE_WIDTH_X32 2 +#define CHX_DEVICE_WIDTH_X64 3 + +#define CHX_DEVICE_DENSITY_4GB 0 +#define CHX_DEVICE_DENSITY_6GB 1 +#define CHX_DEVICE_DENSITY_8GB 2 +#define CHX_DEVICE_DENSITY_12GB 3 +#define CHX_DEVICE_DENSITY_16GB 4 +#define CHX_DEVICE_DENSITY_2GB 5 + +#define CHX_OPTION_RANK_INTERLEAVING 0x1 +#define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2 +#define CHX_OPTION_CH1_CLK_DISABLE 0x4 +#define CHX_OPTION_ADDRESS_MAP_2KB 0x10 + +#define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1 +#define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2 +#define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10 + +#define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0 +#define CHX_ODT_LEVELS_HELD_HIGH 0x1 + +#define NPK_EN_DISABLE 0 +#define NPK_EN_ENABLE 1 +#define NPK_EN_DEBUGGER 2 +#define NPK_EN_AUTO 3 + +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2 +#define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3 +#define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4 + +#define MSC_X_WRAP_0 0 +#define MSC_X_WRAP_1 1 + +#define MSC_X_SIZE_0M 0 +#define MSC_X_SIZE_1M 1 +#define MSC_X_SIZE_8M 2 +#define MSC_X_SIZE_64M 3 +#define MSC_X_SIZE_128M 4 +#define MSC_X_SIZE_256M 5 +#define MSC_X_SIZE_512M 6 +#define MSC_X_SIZE_1GB 7 + +#define PTI_MODE_0 0 +#define PTI_MODE_x4 1 +#define PTI_MODE_x8 2 +#define PTI_MODE_x12 3 +#define PTI_MODE_x16 4 + +#define PTI_SPEED_FULL 0 +#define PTI_SPEED_HALF 1 +#define PTI_SPEED_QUARTER 2 #endif -- 2.25.1
