On Wed, 2020-04-22 at 11:26 +0200, Nicolas Saenz Julienne wrote: > On Wed, 2020-04-22 at 17:21 +0800, Bin Meng wrote: > > Hi Nicolas, > > > > On Wed, Apr 22, 2020 at 4:53 PM Nicolas Saenz Julienne > > <[email protected]> wrote: > > > Hi Sylwester, Marek > > > > > > On Tue, 2020-04-21 at 18:50 +0200, Sylwester Nawrocki wrote: > > > > In current code there is no cache flush after initializing the > > > > scratchpad > > > > buffer array with the scratchpad buffer pointers. This leads to a > > > > failure > > > > of the "slot enable" command on the rpi4 board (Broadcom STB PCIe > > > > controller + VL805 USB hub) - the very first TRB transfer on the command > > > > ring fails and there is a timeout while waiting for the command > > > > completion > > > > event. After adding the missing cache flush everything seems to be > > > > working > > > > as expected. > > > > > > > > Signed-off-by: Sylwester Nawrocki <[email protected]> > > > > Reviewed-by: Bin Meng <[email protected]> > > > > --- > > > > > > I've been trying to get this working on my own and got stuck with this > > > specific > > > issue. I'm glad you found a solution, it was driving me crazy. > > > > > > Out of curiosity how did you found the solution? > > > > > > > drivers/usb/host/xhci-mem.c | 3 +++ > > > > 1 file changed, 3 insertions(+) > > > > > > > > diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c > > > > index 93450ee..729bdc3 100644 > > > > --- a/drivers/usb/host/xhci-mem.c > > > > +++ b/drivers/usb/host/xhci-mem.c > > > > @@ -393,6 +393,9 @@ static int xhci_scratchpad_alloc(struct xhci_ctrl > > > > *ctrl) > > > > scratchpad->sp_array[i] = cpu_to_le64(ptr); > > > > } > > > > > > > > + xhci_flush_cache((uintptr_t)scratchpad->sp_array, > > > > + sizeof(u64) * num_sp); > > > > + > > > > > > Marek, souldn't running 'dcache off; icache off' be equivalent to this > > > (which > > > didn't do the trick for me)? or am I missing somthing? > > > > I guess something is wrong with RPi4's "dcache off" command .. > > You can't trust anything these times :) > > I'll look into it.
Well it's not only that disabling the caches was needed, but also avoiding 64bit accesses, since I was missed that one, I didn't see the change in behavior. In other words, dcache/icache commands are fine. Sorry for the noise. Regards, Nicolas
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