> Subject: RE: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes > > >-----Original Message----- > >From: Ioana Ciornei <[email protected]> > >Sent: Wednesday, March 18, 2020 8:18 PM > >To: Priyanka Jain <[email protected]>; [email protected]; u- > >[email protected] > >Cc: Florin Laurentiu Chiculita <[email protected]>; > >Ioana Ciornei <[email protected]> > >Subject: [PATCH v2 10/14] arm: dts: ls2088ardb: add DPMAC and PHY nodes > > > >In order to maintain compatibility with the Linux DTS, the entire > >fsl-mc node is added but instead of being probed by a dedicated bus > >driver it will be a simple-mfd. > > > >Also, annotate the external MDIO nodes and describe the PHYs (4 x > >AQR405 and 4 x CS4340). Also, add phy-handles for the dpmacs to their > >associated PHY. > > > >Signed-off-by: Ioana Ciornei <[email protected]> > >--- > >Changes in v2: > > - none > > > > arch/arm/dts/fsl-ls2080a.dtsi | 75 +++++++++++++++++++++-- > > arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 88 +++++++++++++++++++++++++++ > > 2 files changed, 157 insertions(+), 6 deletions(-) > > > >diff --git a/arch/arm/dts/fsl-ls2080a.dtsi > >b/arch/arm/dts/fsl-ls2080a.dtsi index > >7ff854caecd5..fb5777e268e4 100644 > >--- a/arch/arm/dts/fsl-ls2080a.dtsi > >+++ b/arch/arm/dts/fsl-ls2080a.dtsi > >@@ -50,12 +50,6 @@ > > interrupts = <0 32 0x1>; /* edge triggered */ > > }; > > > >- fsl_mc: fsl-mc@80c000000 { > >- compatible = "fsl,qoriq-mc"; > >- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal > >base */ > >- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ > >- }; > >- > > i2c0: i2c@2000000 { > > status = "disabled"; > > compatible = "fsl,vf610-i2c"; > >@@ -200,6 +194,75 @@ > > status = "disabled"; > > }; > > > >+ fsl_mc: fsl-mc@80c000000 { > >+ compatible = "fsl,qoriq-mc", "simple-mfd"; > >+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base > >*/ > >+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ > >+ #address-cells = <3>; > >+ #size-cells = <1>; > >+ > >+ /* > >+ * Region type 0x0 - MC portals > >+ * Region type 0x1 - QBMAN portals > >+ */ > >+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 > >+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; > >+ > >+ dpmacs { > >+ compatible = "simple-mfd"; > >+ #address-cells = <1>; > >+ #size-cells = <0>; > >+ > >+ dpmac1: dpmac@1 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x1>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac2: dpmac@2 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x2>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac3: dpmac@3 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x3>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac4: dpmac@4 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x4>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac5: dpmac@5 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x5>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac6: dpmac@6 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x6>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac7: dpmac@7 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x7>; > >+ status = "disabled"; > >+ }; > >+ > >+ dpmac8: dpmac@8 { > >+ compatible = "fsl,qoriq-mc-dpmac"; > >+ reg = <0x8>; > >+ status = "disabled"; > >+ }; > >+ }; > >+ }; > >+ > > emdio1: mdio@8B96000 { > > compatible = "fsl,ls-mdio"; > > reg = <0x0 0x8B96000 0x0 0x1000>; > >diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > >b/arch/arm/dts/fsl-ls2088a- rdb-qspi.dts index > >72b2177b70d9..16b9aeec966c 100644 > >--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > >+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts > >@@ -21,6 +21,94 @@ > > }; > > }; > > > >+&dpmac1 { > >+ status = "okay"; > >+ phy-handle = <&mdio1_phy1>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac2 { > >+ status = "okay"; > >+ phy-handle = <&mdio1_phy2>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac3 { > >+ status = "okay"; > >+ phy-handle = <&mdio1_phy3>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac4 { > >+ status = "okay"; > >+ phy-handle = <&mdio1_phy4>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac5 { > >+ status = "okay"; > >+ phy-handle = <&mdio2_phy1>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac6 { > >+ status = "okay"; > >+ phy-handle = <&mdio2_phy2>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac7 { > >+ status = "okay"; > >+ phy-handle = <&mdio2_phy3>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&dpmac8 { > >+ status = "okay"; > >+ phy-handle = <&mdio2_phy4>; > >+ phy-connection-type = "xfi"; > >+}; > >+ > >+&emdio1 { > >+ status = "okay"; > >+ > >+ /* CS4340 PHYs */ > >+ mdio1_phy1: emdio1_phy@1 { > >+ reg = <0x10>; > >+ }; > >+ mdio1_phy2: emdio1_phy@2 { > >+ reg = <0x11>; > >+ }; > >+ mdio1_phy3: emdio1_phy@3 { > >+ reg = <0x12>; > >+ }; > >+ mdio1_phy4: emdio1_phy@4 { > >+ reg = <0x13>; > >+ }; > >+}; > >+ > >+&emdio2 { > >+ status = "okay"; > >+ > >+ /* AQR405 PHYs */ > >+ mdio2_phy1: emdio2_phy@1 { > >+ compatible = "ethernet-phy-ieee802.3-c45"; > >+ reg = <0x0>; > >+ }; > >+ mdio2_phy2: emdio2_phy@2 { > >+ compatible = "ethernet-phy-ieee802.3-c45"; > >+ reg = <0x1>; > >+ }; > >+ mdio2_phy3: emdio2_phy@3 { > >+ compatible = "ethernet-phy-ieee802.3-c45"; > >+ reg = <0x2>; > >+ }; > >+ mdio2_phy4: emdio2_phy@4 { > >+ compatible = "ethernet-phy-ieee802.3-c45"; > >+ reg = <0x3>; > >+ }; > >+}; > >+ > > &dspi { > > bus-num = <0>; > > status = "okay"; > >-- > >2.17.1 > Similar changes will be required in ls2080a board files as well which also > include > fsl-ls2080a.dtsi like fsl-ls2080a-rdb.dts, fsl-ls2080a-qds.dts
The QDS boards are handled in another patch set. For the LS2080ARDB (fsl-ls2080a-rdb.dts) do you want to submit a separate patch? Ioana > > Regards > Priyanka
