> -----Original Message-----
> From: Tan, Ley Foon <[email protected]>
> Sent: Monday, April 20, 2020 4:17 PM
> To: [email protected]
> Cc: Marek Vasut <[email protected]>; Ley Foon Tan <[email protected]>;
> See, Chin Liang <[email protected]>; Simon Goldschmidt
> <[email protected]>; Ang, Chee Hong
> <[email protected]>; Tan, Ley Foon <[email protected]>
> Subject: [PATCH] arm: socfpga: stratix10: Fix incorrect
> CLKMGR_S10_PERPLL_BYPASS offset
>
> Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.
>
> Reported-by: Chee Hong Ang <[email protected]>
> Signed-off-by: Ley Foon Tan <[email protected]>
> ---
> arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index e710aa2f94f0..9d2b3bababe2 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -85,7 +85,7 @@ void cm_basic_init(const struct cm_config * const cfg);
> #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
> /* Periphpll group */
> #define CLKMGR_S10_PERPLL_EN 0xa4
> -#define CLKMGR_S10_PERPLL_BYPASS 0xac
> +#define CLKMGR_S10_PERPLL_BYPASS 0xb0
> #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
> #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
> #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
> --
Any comment on this patch?
Thanks.
Regards
Ley Foon
