> Subject: RE: [PATCH 3/6] arm: dts: lx2160aqds: add nodes describing possible
> mezzanine cards
>
> >-----Original Message-----
> >From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of Ioana Ciornei
> >Sent: Wednesday, April 22, 2020 10:39 PM
> >To: Priyanka Jain <priyanka.j...@nxp.com>; u-boot@lists.denx.de
> >Cc: Alexandru Marginean <alexandru.margin...@nxp.com>; Madalin Bucur
> ><madalin.bu...@nxp.com>; Florin Laurentiu Chiculita
> ><florinlaurentiu.chicul...@nxp.com>; Razvan Ionut Cirjan
> ><razvanionut.cir...@nxp.com>; Ioana Ciornei <ioana.cior...@nxp.com>
> >Subject: [PATCH 3/6] arm: dts: lx2160aqds: add nodes describing
> >possible mezzanine cards
> >
> >Add device trees describing possible uses of mezzanine cards depending
> >on the SERDES protocol employed.
> >
> >Each SERDES block has a different device tree file per protocol
> >supported, where the IO SLOTs used are enabled and PHYs located on the
> >mezzanine cards are described. Also, dpmac nodes are edited and their
> >associated phy- connection-type and phy-handle are added.
> >
> >Top DTS files are also added for each combination of protocol on the 3
> >SERDES blocks.
> Please mention serdes protocols list for which you are adding the support
Sure, I'll add that in v2.
> >
> >Signed-off-by: Ioana Ciornei <ioana.cior...@nxp.com>
> >---
> > arch/arm/dts/Makefile | 10 +-
> > arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl-
> >lx2160a-qds-19-x-x.dts | 17 +++
> >arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts |
> >19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++
> >arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts | 19 +++
> > arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++
> > arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++
> > arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++
> > arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++++
> >arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi | 39 +++++
> >arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
> >| 55 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100
> >| +++++++++++++
> >arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 ++++++++++
> > arch/arm/dts/fsl-lx2160a-qds.dts | 180 +----------------------
> > arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++
> > 16 files changed, 670 insertions(+), 178 deletions(-) create mode
> >100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
> > create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi
> >
> >diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index
> >6d1e8668e7ee..4fe042dbd7ee 100644
> >--- a/arch/arm/dts/Makefile
> >+++ b/arch/arm/dts/Makefile
> >@@ -377,7 +377,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
> > fsl-ls1028a-rdb.dtb \
> > fsl-ls1028a-qds.dtb \
> > fsl-lx2160a-rdb.dtb \
> >- fsl-lx2160a-qds.dtb
> >+ fsl-lx2160a-qds.dtb \
> >+ fsl-lx2160a-qds-3-x-x.dtb \
> >+ fsl-lx2160a-qds-3-11-x.dtb \
> >+ fsl-lx2160a-qds-7-x-x.dtb \
> >+ fsl-lx2160a-qds-7-11-x.dtb \
> >+ fsl-lx2160a-qds-19-x-x.dtb \
> >+ fsl-lx2160a-qds-19-11-x.dtb \
> >+ fsl-lx2160a-qds-20-x-x.dtb \
> >+ fsl-lx2160a-qds-20-11-x.dtb
> > dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
> > fsl-ls1043a-qds-lpuart.dtb \
> > fsl-ls1043a-rdb.dtb \
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-19-11-x.dts new file mode 100644 index
> >000000000000..585759162f6c
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
> >@@ -0,0 +1,19 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-19.dtsi"
> >+
> >+#include "fsl-lx2160a-qds-sd2-11.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-19-x-x.dts new file mode 100644 index
> >000000000000..ebe11396a6cb
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
> >@@ -0,0 +1,17 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-19.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-20-11-x.dts new file mode 100644 index
> >000000000000..d9f091896746
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
> >@@ -0,0 +1,19 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-20.dtsi"
> >+
> >+#include "fsl-lx2160a-qds-sd2-11.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-20-x-x.dts new file mode 100644 index
> >000000000000..735d440d3737
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
> >@@ -0,0 +1,17 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-20.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-3-11-x.dts new file mode 100644 index
> >000000000000..3b21c87b9329
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
> >@@ -0,0 +1,19 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-3.dtsi"
> >+
> >+#include "fsl-lx2160a-qds-sd2-11.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl-
> >lx2160a-qds-3-x-x.dts new file mode 100644 index
> >000000000000..ede40563f71e
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
> >@@ -0,0 +1,17 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-3.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
> >b/arch/arm/dts/fsl- lx2160a-qds-7-11-x.dts new file mode 100644 index
> >000000000000..8100af47271a
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
> >@@ -0,0 +1,19 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-7.dtsi"
> >+
> >+#include "fsl-lx2160a-qds-sd2-11.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl-
> >lx2160a-qds-7-x-x.dts new file mode 100644 index
> >000000000000..15dee3587f91
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
> >@@ -0,0 +1,17 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+/dts-v1/;
> >+
> >+#include "fsl-lx2160a-qds-sd1-7.dtsi"
> >+
> >+/ {
> >+ model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
> >+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
> >+
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
> >b/arch/arm/dts/fsl- lx2160a-qds-sd1-19.dtsi new file mode 100644 index
> >000000000000..a31ff8a1bd85
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
> >@@ -0,0 +1,75 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for the SERDES block #1 -
> >+protocol
> >+19
> >+ *
> >+ * Some assumptions are made:
> >+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
> >+ * * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
> >+ * * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+#include "fsl-lx2160a-qds.dtsi"
> >+
> >+&dpmac2 {
> >+ status = "okay";
> >+ phy-handle = <&cortina_phy0>;
> >+ phy-connection-type = "xlaui4";
> >+};
> >+
> >+&dpmac3 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy1>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac4 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy2>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac5 {
> >+ status = "okay";
> >+ phy-handle = <&inphi_phy0>;
> >+ phy-connection-type = "25g-aui";
> >+};
> >+
> >+&dpmac6 {
> >+ status = "okay";
> >+ phy-handle = <&inphi_phy1>;
> >+ phy-connection-type = "25g-aui";
> >+};
> >+
> >+&emdio1_slot1 {
> >+ aquantia_phy1: ethernet-phy@4 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+
> >+ aquantia_phy2: ethernet-phy@5 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x1>;
> >+ };
> >+};
> >+
> >+&emdio1_slot2 {
> >+ cortina_phy0: ethernet-phy@0 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+};
> >+
> >+&emdio1_slot6 {
> >+ inphi_phy0: ethernet-phy@0 {
> >+ compatible = "ethernet-phy-id0210.7440";
> >+ reg = <0x0>;
> >+ };
> >+
> >+ inphi_phy1: ethernet-phy@1 {
> >+ compatible = "ethernet-phy-id0210.7440";
> >+ reg = <0x1>;
> >+ };
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
> >b/arch/arm/dts/fsl- lx2160a-qds-sd1-20.dtsi new file mode 100644 index
> >000000000000..42e149691d5b
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
> >@@ -0,0 +1,39 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for the SERDES block #1 -
> >+protocol
> >+20
> >+ *
> >+ * Some assumptions are made:
> >+ * * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
> >+ * (xlaui4 for DPMAC 1,2)
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+#include "fsl-lx2160a-qds.dtsi"
> >+
> >+&dpmac1 {
> >+ status = "okay";
> >+ phy-handle = <&cortina_phy1_0>;
> >+ phy-connection-type = "xlaui4";
> >+};
> >+
> >+&dpmac2 {
> >+ status = "okay";
> >+ phy-handle = <&cortina_phy2_0>;
> >+ phy-connection-type = "xlaui4";
> >+};
> >+
> >+&emdio1_slot1 {
> >+ cortina_phy1_0: ethernet-phy@0 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+};
> >+
> >+&emdio1_slot2 {
> >+ cortina_phy2_0: ethernet-phy@0 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
> >b/arch/arm/dts/fsl- lx2160a-qds-sd1-3.dtsi new file mode 100644 index
> >000000000000..256d784aca84
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
> >@@ -0,0 +1,55 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for the SERDES block #1 -
> >+protocol
> >+3
> >+ *
> >+ * Some assumptions are made:
> >+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
> >3,4,5,6)
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+
> >+#include "fsl-lx2160a-qds.dtsi"
> >+
> >+&dpmac3 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy1>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac4 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy2>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac5 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy3>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac6 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy4>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&emdio1_slot1 {
> >+ aquantia_phy1: ethernet-phy@4 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+ aquantia_phy2: ethernet-phy@5 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x1>;
> >+ };
> >+ aquantia_phy3: ethernet-phy@6 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x2>;
> >+ };
> >+ aquantia_phy4: ethernet-phy@7 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x3>;
> >+ };
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
> >b/arch/arm/dts/fsl- lx2160a-qds-sd1-7.dtsi new file mode 100644 index
> >000000000000..5fcf846c1066
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
> >@@ -0,0 +1,100 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for the SERDES block #1 -
> >+protocol
> >+7
> >+ *
> >+ * Some assumptions are made:
> >+ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC
> >3,4,5,6)
> >+ * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC
> >7,8,9,10)
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+#include "fsl-lx2160a-qds.dtsi"
> >+
> >+&dpmac3 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy1>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac4 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy2>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac5 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy3>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac6 {
> >+ status = "okay";
> >+ phy-handle = <&aquantia_phy4>;
> >+ phy-connection-type = "usxgmii";
> >+};
> >+
> >+&dpmac7 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy1>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac8 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy2>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac9 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy3>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac10 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy4>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&emdio1_slot1 {
> >+ aquantia_phy1: ethernet-phy@4 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x0>;
> >+ };
> >+
> >+ aquantia_phy2: ethernet-phy@5 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x1>;
> >+ };
> >+
> >+ aquantia_phy3: ethernet-phy@6 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x2>;
> >+ };
> >+
> >+ aquantia_phy4: ethernet-phy@7 {
> >+ compatible = "ethernet-phy-ieee802.3-c45";
> >+ reg = <0x3>;
> >+ };
> >+};
> >+
> >+&emdio1_slot2 {
> >+ sgmii_phy1: ethernet-phy@1c {
> >+ reg = <0x1c>;
> >+ };
> >+
> >+ sgmii_phy2: ethernet-phy@1d {
> >+ reg = <0x1d>;
> >+ };
> >+
> >+ sgmii_phy3: ethernet-phy@1e {
> >+ reg = <0x1e>;
> >+ };
> >+
> >+ sgmii_phy4: ethernet-phy@1f {
> >+ reg = <0x1f>;
> >+ };
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
> >b/arch/arm/dts/fsl- lx2160a-qds-sd2-11.dtsi new file mode 100644 index
> >000000000000..cf09f98aa60f
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
> >@@ -0,0 +1,76 @@
> >+// SPDX-License-Identifier: GPL-2.0+ OR X11
> >+/*
> >+ * NXP LX2160AQDS device tree source for the SERDES block #2 -
> >+protocol
> >+11
> >+ *
> >+ * Some assumptions are made:
> >+ * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
> >+ * (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
> >+ *
> >+ * Copyright 2020 NXP
> >+ *
> >+ */
> >+#include "fsl-lx2160a-qds.dtsi"
> >+
> >+&dpmac12 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy7_2>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac17 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy7_3>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac18 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy7_4>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac16 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy8_2>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac13 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy8_3>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&dpmac14 {
> >+ status = "okay";
> >+ phy-handle = <&sgmii_phy8_4>;
> >+ phy-connection-type = "sgmii";
> >+};
> >+
> >+&emdio1_slot7 {
> >+ sgmii_phy7_2: ethernet-phy@1d {
> >+ reg = <0x1d>;
> >+ };
> >+
> >+ sgmii_phy7_3: ethernet-phy@1e {
> >+ reg = <0x1e>;
> >+ };
> >+
> >+ sgmii_phy7_4: ethernet-phy@1f {
> >+ reg = <0x1f>;
> >+ };
> >+};
> >+
> >+&emdio1_slot8 {
> >+ sgmii_phy8_2: ethernet-phy@1d {
> >+ reg = <0x1d>;
> >+ };
> >+
> >+ sgmii_phy8_3: ethernet-phy@1e {
> >+ reg = <0x1e>;
> >+ };
> >+
> >+ sgmii_phy8_4: ethernet-phy@1f {
> >+ reg = <0x1f>;
> >+ };
> >+};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts
> >b/arch/arm/dts/fsl-lx2160a- qds.dts index 4946ce8dfba8..e0f5d5e2d38f
> >100644
> >--- a/arch/arm/dts/fsl-lx2160a-qds.dts
> >+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
> >@@ -1,14 +1,14 @@
> > // SPDX-License-Identifier: GPL-2.0+ OR X11
> > /*
> >- * NXP LX2160AQDS device tree source
> >+ * NXP LX2160AQDS default device tree source
> > *
> >- * Copyright 2018-2020 NXP
> >+ * Copyright 2020 NXP
> > *
> > */
> >
> > /dts-v1/;
> >
> >-#include "fsl-lx2160a.dtsi"
> >+#include "fsl-lx2160a-qds.dtsi"
> >
> > / {
> > model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@
> > spi0 = &fspi;
> > };
> > };
> >-
> >-&dpmac17 {
> >- status = "okay";
> >- phy-handle = <&rgmii_phy1>;
> >- phy-connection-type = "rgmii-id";
> >-};
> >-
> >-&dpmac18 {
> >- status = "okay";
> >- phy-handle = <&rgmii_phy2>;
> >- phy-connection-type = "rgmii-id";
> >-};
> >-
> >-&emdio1 {
> >- status = "okay";
> >-};
> >-
> >-&emdio2 {
> >- status = "okay";
> >-};
> >-
> >-&esdhc0 {
> >- status = "okay";
> >-};
> >-
> >-&esdhc1 {
> >- status = "okay";
> >-};
> >-
> >-&i2c0 {
> >- status = "okay";
> >- u-boot,dm-pre-reloc;
> >-
> >- fpga@66 {
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- compatible = "simple-mfd";
> >- reg = <0x66>;
> >-
> >- mux-mdio@54 {
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- compatible = "mdio-mux-i2creg";
> >- reg = <0x54>;
> >- #mux-control-cells = <1>;
> >- mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
> >- mdio-parent-bus = <&emdio1>;
> >-
> >- mdio@00 {
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- reg = <0x00>;
> >-
> >- rgmii_phy1: ethernet-phy@1 {
> >- reg = <0x1>;
> >- };
> >- };
> >- mdio@08 {
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- reg = <0x40>;
> >-
> >- rgmii_phy2: ethernet-phy@2 {
> >- reg = <0x2>;
> >- };
> >- };
> >-
> >- emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
> >- reg = <0xC0>;
> >- device-name = "emdio1_slot1";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
> >- reg = <0xC8>;
> >- device-name = "emdio1_slot2";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
> >- reg = <0xD0>;
> >- device-name = "emdio1_slot3";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
> >- reg = <0xD8>;
> >- device-name = "emdio1_slot4";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
> >- reg = <0xE0>;
> >- device-name = "emdio1_slot5";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
> >- reg = <0xE8>;
> >- device-name = "emdio1_slot6";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
> >- reg = <0xF0>;
> >- device-name = "emdio1_slot7";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >-
> >- emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
> >- reg = <0xF8>;
> >- device-name = "emdio1_slot8";
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- };
> >- };
> >-
> >- };
> >-
> >- i2c-mux@77 {
> >- compatible = "nxp,pca9547";
> >- reg = <0x77>;
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >-
> >- i2c@3 {
> >- #address-cells = <1>;
> >- #size-cells = <0>;
> >- reg = <0x3>;
> >-
> >- rtc@51 {
> >- compatible = "pcf2127-rtc";
> >- reg = <0x51>;
> >- };
> >- };
> >- };
> >-};
> >-
> >-&fspi {
> >- status = "okay";
> >-
> >- mt35xu512aba0: flash@0 {
> >- #address-cells = <1>;
> >- #size-cells = <1>;
> >- compatible = "jedec,spi-nor";
> >- spi-max-frequency = <50000000>;
> >- reg = <0>;
> >- spi-rx-bus-width = <8>;
> >- spi-tx-bus-width = <1>;
> >- };
> >-};
> >-
> >-&sata0 {
> >- status = "okay";
> >-};
> >-
> >-&sata1 {
> >- status = "okay";
> >-};
> >-
> >-&sata2 {
> >- status = "okay";
> >-};
> >-
> >-&sata3 {
> >- status = "okay";
> >-};
> >diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
> >b/arch/arm/dts/fsl-lx2160a- qds.dtsi new file mode 100644 index
> >000000000000..129cf82a8f37
> >--- /dev/null
> >+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
> <snip>
>
> Is there any particular reason of adding dpmac related changes in one file in
> previous patch And then putting in another fie in next patch. Cant we squash
> this
> change with the previous patch?
>
Not a particular strong reason, I was just thinking that it's cleaner.
I'll squash them.
Thanks,
Ioana
> Regards
> Priyanka
