> -----Original Message-----
> From: Z.q. Hou <[email protected]>
> Sent: Tuesday, April 28, 2020 7:49 AM
> To: [email protected]; Priyanka Jain <[email protected]>; Wasim Khan
> <[email protected]>; [email protected]
> Cc: Z.q. Hou <[email protected]>
> Subject: [PATCHv3 1/8] arm64: fsl-layerscape: Assign addr to resv_ram if
> enabled RESV_RAM config
>
> From: Hou Zhiqiang <[email protected]>
>
> The initialization of gd->arch.resv_ram pointer should depend on if the
> RESV_RAM config is enabled.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
Reviewed-by: Wasim Khan <[email protected]>
> ---
> V3:
> - No change.
>
> arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index b443894453..1b7729c046 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
> if (i > 0)
> ret = 0;
>
> -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> /* Assign memory for MC */
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> if (gd->bd->bi_dram[2].size >=
> @@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
> board_reserve_ram_top(gd->bd-
> >bi_dram[0].size);
> }
> }
> -#endif /* CONFIG_FSL_MC_ENET */
> +#endif /* CONFIG_RESV_RAM */
>
> return ret;
> }
> @@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
> }
> #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
>
> -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
> +#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
> /* Assign memory for MC */
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> if (gd->bd->bi_dram[2].size >=
> @@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
> board_reserve_ram_top(gd->bd-
> >bi_dram[0].size);
> }
> }
> -#endif /* CONFIG_FSL_MC_ENET */
> +#endif /* CONFIG_RESV_RAM */
>
> #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
> #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
> --
> 2.17.1
