On 4/28/20 8:27 AM, Frank Wang wrote: > RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller > in resetting to hold pipe power state in P2 before initializing the PHY. > This commit fixed it and added device compatible for rockchip platform. > > Signed-off-by: Frank Wang <[email protected]> > --- > drivers/usb/dwc3/dwc3-generic.c | 33 +++++++++++++++++++++++++++------ > 1 file changed, 27 insertions(+), 6 deletions(-) > > diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c > index febcfc0f54..0031e8bf44 100644 > --- a/drivers/usb/dwc3/dwc3-generic.c > +++ b/drivers/usb/dwc3/dwc3-generic.c > @@ -24,6 +24,12 @@ > #include <clk.h> > #include <usb/xhci.h> > > +struct dwc3_glue_data { > + struct clk_bulk clks; > + struct reset_ctl_bulk resets; > + fdt_addr_t regs; > +}; > + > struct dwc3_generic_plat { > fdt_addr_t base; > u32 maximum_speed; > @@ -48,6 +54,7 @@ static int dwc3_generic_probe(struct udevice *dev, > int rc; > struct dwc3_generic_plat *plat = dev_get_platdata(dev); > struct dwc3 *dwc3 = &priv->dwc3; > + struct dwc3_glue_data *glue = dev_get_platdata(dev->parent); > > dwc3->dev = dev; > dwc3->maximum_speed = plat->maximum_speed; > @@ -56,10 +63,22 @@ static int dwc3_generic_probe(struct udevice *dev, > dwc3_of_parse(dwc3); > #endif > > + /* > + * It must hold whole USB3.0 OTG controller in resetting to hold pipe > + * power state in P2 before initializing TypeC PHY on RK3399 platform. > + */ > + if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) { > + reset_assert_bulk(&glue->resets); > + udelay(1);
Reset delay should be handled by the reset controller, no ?
