On Fri, Apr 24, 2020 at 08:20:17PM +0200, Patrick Delaunay wrote: > Solved the overflow on phys_addr_t type for start + size in > mmu_set_region_dcache_behaviour() function. > > This overflow is avoided by dividing start and end by 2 before addition, > and we only expecting that start and size are even. > > This patch doesn't change the current function behavior if the > parameters (start or size) are not aligned on MMU_SECTION_SIZE. > > For example, this overflow occurs on ARM32 with: > start = 0xC0000000 and size = 0x40000000 > then start + size = 0x100000000 and end = 0x0. > > For information the function behavior change with risk of regression, > if we just shift start and size before the addition. > Example with 2MB section size: > MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21 > with start = 0x1000000, size = 0x1000000, > - with the proposed patch, start = 0 and end = 0x1 as previously > - with the more simple patch: > end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT) > the value of end change: > start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!! > > Signed-off-by: Patrick Delaunay <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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