Try to get USB working with imx8qm. Therefore I took below from NXP
vendor tree. Can someone point me to the missing driver parts that are
needed?

Best regards,

Oliver

---
 arch/arm/dts/fsl-imx8qm.dtsi | 71 ++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 6808f68f9d..87c3bb2257 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -40,6 +40,10 @@
                i2c1 = &i2c1;
                i2c2 = &i2c2;
                i2c3 = &i2c3;
+               usb0 = &usbotg1;
+               usbphy0 = &usbphy1;
+               usb1 = &usb2;
+               usbphy1 = &usb2_phy;
                i2c4 = &i2c4;
        };
 
@@ -142,6 +146,33 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
 
+                       pd_conn_usbotg0: PD_CONN_USB_0 {
+                               reg = <SC_R_USB_0>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_conn>;
+                       };
+
+                       pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
+                               reg = <SC_R_USB_0_PHY>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_conn>;
+                       };
+
+                       pd_conn_usbotg1: PD_CONN_USB_1 {
+                               reg = <SC_R_USB_1>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_conn>;
+                       };
+                       pd_conn_usb2: PD_CONN_USB_2 {
+                               reg = <SC_R_USB_2>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_conn>;
+                       };
+                       pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
+                               reg = <SC_R_USB_2_PHY>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_conn>;
+                       };
                        pd_conn_sdch0: PD_CONN_SDHC_0 {
                                reg = <SC_R_SDHC_0>;
                                #power-domain-cells = <0>;
@@ -555,6 +586,46 @@
                power-domains = <&pd_conn_enet1>;
                status = "disabled";
        };
+
+       usbmisc1: usbmisc@5b0d0200 {
+               #index-cells = <1>;
+               compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+               reg = <0x0 0x5b0d0200 0x0 0x200>;
+       };
+
+       usbphy1: usbphy@0x5b100000 {
+               compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", 
"fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+               reg = <0x0 0x5b100000 0x0 0x200>;
+               clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
+               power-domains = <&pd_conn_usbotg0_phy>;
+       };
+
+       usbotg1: usb@5b0d0000 {
+               compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+               reg = <0x0 0x5b0d0000 0x0 0x200>;
+               interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+               fsl,usbphy = <&usbphy1>;
+               fsl,usbmisc = <&usbmisc1 0>;
+               clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
+               phy-clkgate-delay-us = <400>;
+               status = "disabled";
+               #stream-id-cells = <1>;
+               power-domains = <&pd_conn_usbotg0>;
+       };
+
+       usb2_phy: phy@0x5b160000 {
+               compatible = "fsl,imx8-usb-phy";
+               reg = <0x0 0x5b160000 0x0 0x10000>;
+               power-domains = <&pd_conn_usb2_phy>;
+       };
+
+       usb2: usb@0x5b110000 {
+               compatible = "fsl,imx8-usb3";
+               reg = <0x0 0x5b110000 0x0 0x38000>;
+               fsl,usbphy = <&usb2_phy>;
+               status = "disabled";
+               power-domains = <&pd_conn_usb2>;
+       };
 };
 
 &A53_0 {
-- 
2.17.1

Reply via email to