Re: [PATCH v1 03/10] mips: cache: Don't use cache operations with CONFIG_MIPS_CACHE_COHERENT

[Stefan Roese]

On 13.05.20 15:05, Daniel Schwierzeck wrote:

Am 02.05.20 um 10:59 schrieb Stefan Roese:

The Octeon platform is cache coherent and cache flushes and invalidates
are not needed. This patch makes use of the newly introduced Kconfig
option CONFIG_MIPS_CACHE_COHERENT to effectively disable all the cache
operations.

I don't like this extra config option. Only flush_dcache_range() is
called from generic MIPS code. You could simply add an empty function
implementation to mach-octeon/ because it's already annotated as __weak.
The other functions should be irrelevant if not used in any driver.

Okay. I've noticed though, that calling flush_cache() from reloc.c
breaks the port. So I would like to make flush_cache() also __weak
and add the empty flush_cache() function to the Octeon base port
as well.

Thanks,
Stefan

Signed-off-by: Stefan Roese <s...@denx.de>
---

  arch/mips/lib/cache.c | 38 ++++++++++++++++++++++++++++++--------
  1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 9e20b39608..e27826cbb1 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -118,6 +118,7 @@ static inline unsigned long scache_line_size(void)
        }                                                               \
  } while (0)

+#if !defined(CONFIG_MIPS_CACHE_COHERENT)

  void flush_cache(ulong start_addr, ulong size)
  {
        unsigned long ilsize = icache_line_size();
@@ -188,6 +189,35 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        sync();
  }

+void dcache_disable(void)

+{
+       /* change CCA to uncached */
+       change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+       /* ensure the pipeline doesn't contain now-invalid instructions */
+       instruction_hazard_barrier();
+}
+
+#else /* CONFIG_MIPS_CACHE_COHERENT */
+
+void flush_cache(ulong start_addr, ulong size)
+{
+}
+
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+#endif /* CONFIG_MIPS_CACHE_COHERENT */
+
  int dcache_status(void)
  {
        unsigned int cca = read_c0_config() & CONF_CM_CMASK;
@@ -199,11 +229,3 @@ void dcache_enable(void)
        puts("Not supported!\n");
  }

-void dcache_disable(void)

-{
-       /* change CCA to uncached */
-       change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-
-       /* ensure the pipeline doesn't contain now-invalid instructions */
-       instruction_hazard_barrier();
-}

Viele Grüße,
Stefan

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